From 14c51c0259d242089276cc37e1b9c57d6c4ad1da Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Mon, 27 Dec 2010 15:34:59 +0530 Subject: [PATCH] [ARM] tegra: clocks: add clock entry for bsev Change-Id: I7ec657c30b84c65705b38a390bdc44b64cd5ea36 Signed-off-by: Varun Wadekar --- arch/arm/mach-tegra/tegra2_clocks.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 3625b8091c76..b5494ae4c4a2 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -1952,6 +1952,7 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0), PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0), + PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0), PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */ /* FIXME: what is la? */ -- 2.34.1