From 15a6c3e97629c61c8407b57289be53de9237b554 Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Mon, 16 Oct 2006 17:57:20 +0000 Subject: [PATCH] define the IntBinOp class and use it to implement the multiply instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30978 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index e5db101865b..956f16bf78f 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -36,9 +36,8 @@ def iaddr : ComplexPattern; //def raddr : ComplexPattern; //===----------------------------------------------------------------------===// -// Instructions +// Instruction Class Templates //===----------------------------------------------------------------------===// - class InstARM pattern> : Instruction { let Namespace = "ARM"; @@ -47,6 +46,15 @@ class InstARM pattern> : Instruction { let Pattern = pattern; } +class IntBinOp : + InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b), + !strconcat(OpcStr, " $dst, $a, $b"), + [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>; + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + def brtarget : Operand; // Operand for printing out a condition code. @@ -186,18 +194,11 @@ let isTwoAddress = 1 in { IntRegs:$false, imm:$cc))]>; } -def MUL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b), - "mul $dst, $a, $b", - [(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>; +def MUL : IntBinOp<"mul", mul>; let Defs = [R0] in { - def SMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b), - "smull r12, $dst, $a, $b", - [(set IntRegs:$dst, (mulhs IntRegs:$a, IntRegs:$b))]>; - - def UMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b), - "umull r12, $dst, $a, $b", - [(set IntRegs:$dst, (mulhu IntRegs:$a, IntRegs:$b))]>; + def SMULL : IntBinOp<"smull r12,", mulhs>; + def UMULL : IntBinOp<"umull r12,", mulhu>; } def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc), -- 2.34.1