From 17c8fefc9f89a60e4e26006d2dc7389d3e7b73e4 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Fri, 1 Aug 2014 00:32:39 +0000 Subject: [PATCH] R600/SI: Do abs/neg folding with ComplexPatterns Abs/neg folding has moved out of foldOperands and into the instruction selection phase using complex patterns. As a consequence of this change, we now prefer to select the 64-bit encoding for most instructions and the modifier operands have been dropped from integer VOP3 instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214467 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 35 + lib/Target/R600/AMDGPUInstructions.td | 8 + .../R600/MCTargetDesc/SIMCCodeEmitter.cpp | 10 + lib/Target/R600/SIISelLowering.cpp | 32 +- lib/Target/R600/SIInstrFormats.td | 7 + lib/Target/R600/SIInstrInfo.cpp | 54 +- lib/Target/R600/SIInstrInfo.h | 10 + lib/Target/R600/SIInstrInfo.td | 566 +++++++--- lib/Target/R600/SIInstructions.td | 964 ++++++++++-------- lib/Target/R600/SILowerI1Copies.cpp | 4 - lib/Target/R600/SIShrinkInstructions.cpp | 2 +- test/CodeGen/R600/fabs.ll | 3 +- test/CodeGen/R600/fneg.ll | 3 +- test/CodeGen/R600/fsub.ll | 12 +- test/CodeGen/R600/mul_uint24.ll | 4 +- test/CodeGen/R600/vop-shrink.ll | 5 - 16 files changed, 1046 insertions(+), 673 deletions(-) diff --git a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp index cc17b7ec618..090fd1da920 100644 --- a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp +++ b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp @@ -96,6 +96,9 @@ private: SDValue &SOffset, SDValue &Offset, SDValue &Offen, SDValue &Idxen, SDValue &GLC, SDValue &SLC, SDValue &TFE) const; + bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const; + bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods, + SDValue &Clamp, SDValue &Omod) const; SDNode *SelectADD_SUB_I64(SDNode *N); SDNode *SelectDIV_SCALE(SDNode *N); @@ -879,6 +882,38 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFAddr32(SDValue Addr, SDValue &SRsrc, return SelectMUBUFScratch(Addr, SRsrc, VAddr, SOffset, Offset); } +bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src, + SDValue &SrcMods) const { + + unsigned Mods = 0; + + Src = In; + + if (Src.getOpcode() == ISD::FNEG) { + Mods |= SISrcMods::NEG; + Src = Src.getOperand(0); + } + + if (Src.getOpcode() == ISD::FABS) { + Mods |= SISrcMods::ABS; + Src = Src.getOperand(0); + } + + SrcMods = CurDAG->getTargetConstant(Mods, MVT::i32); + + return true; +} + +bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src, + SDValue &SrcMods, SDValue &Clamp, + SDValue &Omod) const { + // FIXME: Handle Clamp and Omod + Clamp = CurDAG->getTargetConstant(0, MVT::i32); + Omod = CurDAG->getTargetConstant(0, MVT::i32); + + return SelectVOP3Mods(In, Src, SrcMods); +} + void AMDGPUDAGToDAGISel::PostprocessISelDAG() { const AMDGPUTargetLowering& Lowering = *static_cast(getTargetLowering()); diff --git a/lib/Target/R600/AMDGPUInstructions.td b/lib/Target/R600/AMDGPUInstructions.td index cd3560378e5..4b8685877d4 100644 --- a/lib/Target/R600/AMDGPUInstructions.td +++ b/lib/Target/R600/AMDGPUInstructions.td @@ -323,6 +323,14 @@ def atomic_cmp_swap_64_local : AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS; }]>; +//===----------------------------------------------------------------------===// +// Misc Pattern Fragments +//===----------------------------------------------------------------------===// + +def fmad : PatFrag < + (ops node:$src0, node:$src1, node:$src2), + (fadd (fmul node:$src0, node:$src1), node:$src2) +>; class Constants { int TWO_PI = 0x40c90fdb; diff --git a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp index 78776c11d75..65f3eb5d99a 100644 --- a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp @@ -14,6 +14,7 @@ //===----------------------------------------------------------------------===// #include "AMDGPU.h" +#include "SIDefines.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "MCTargetDesc/AMDGPUMCCodeEmitter.h" #include "MCTargetDesc/AMDGPUFixupKinds.h" @@ -84,6 +85,15 @@ MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII, bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const { + // FIXME: We need a better way to figure out which operands can be immediate + // values + // + // Some VOP* instructions like ADDC use VReg32 as the register class + // for source 0, because they read VCC and can't take an SGPR as an + // argument due to constant bus restrictions. + if (OpNo == 1 && (Desc.TSFlags & (SIInstrFlags::VOP1 | SIInstrFlags::VOP2 | + SIInstrFlags::VOPC))) + return true; unsigned RegClass = Desc.OpInfo[OpNo].RegClass; return (AMDGPU::SSrc_32RegClassID == RegClass) || diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index c3405e10453..dc26a82e19d 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -566,8 +566,6 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( .addReg(MI->getOperand(1).getReg()) .addImm(1) // SRC1 modifiers .addReg(MI->getOperand(2).getReg()) - .addImm(0) // SRC2 modifiers - .addImm(0) // src2 .addImm(0) // CLAMP .addImm(0); // OMOD MI->eraseFromParent(); @@ -1636,39 +1634,23 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node, continue; if (!Operand.isMachineOpcode()) continue; - if (Operand.getMachineOpcode() == AMDGPU::FNEG_SI) { - Ops.pop_back(); - Ops.push_back(Operand.getOperand(0)); - InputModifiers[i] = 1; - Promote2e64 = true; - if (!DescE64) - continue; - Desc = DescE64; - DescE64 = nullptr; - } - else if (Operand.getMachineOpcode() == AMDGPU::FABS_SI) { - Ops.pop_back(); - Ops.push_back(Operand.getOperand(0)); - InputModifiers[i] = 2; - Promote2e64 = true; - if (!DescE64) - continue; - Desc = DescE64; - DescE64 = nullptr; - } } if (Promote2e64) { std::vector OldOps(Ops); Ops.clear(); + bool HasModifiers = TII->hasModifiers(Desc->Opcode); for (unsigned i = 0; i < OldOps.size(); ++i) { // src_modifier - Ops.push_back(DAG.getTargetConstant(InputModifiers[i], MVT::i32)); + if (HasModifiers) + Ops.push_back(DAG.getTargetConstant(InputModifiers[i], MVT::i32)); Ops.push_back(OldOps[i]); } // Add the modifier flags while promoting - for (unsigned i = 0; i < 2; ++i) - Ops.push_back(DAG.getTargetConstant(0, MVT::i32)); + if (HasModifiers) { + for (unsigned i = 0; i < 2; ++i) + Ops.push_back(DAG.getTargetConstant(0, MVT::i32)); + } } // Add optional chain and glue diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td index 7a89a62f110..db3868ec0d1 100644 --- a/lib/Target/R600/SIInstrFormats.td +++ b/lib/Target/R600/SIInstrFormats.td @@ -61,9 +61,16 @@ class VOP3Common pattern> : let mayStore = 0; let hasSideEffects = 0; let UseNamedOperandTable = 1; + // Using complex patterns gives VOP3 patterns a very high complexity rating, + // but standalone patterns are almost always prefered, so we need to adjust the + // priority lower. The goal is to use a high number to reduce complexity to + // zero (or less than zero). + let AddedComplexity = -1000; + let VOP3 = 1; int Size = 8; + let Uses = [EXEC]; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index 0f93fd7a940..5511fb74e42 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -488,12 +488,19 @@ MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI, return nullptr; } - // XXX: Commute VOP3 instructions with abs and neg set. - if (isVOP3(MI->getOpcode()) && - (MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(), - AMDGPU::OpName::abs)).getImm() || - MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(), - AMDGPU::OpName::neg)).getImm())) + // XXX: Commute VOP3 instructions with abs and neg set . + const MachineOperand *Abs = getNamedOperand(*MI, AMDGPU::OpName::abs); + const MachineOperand *Neg = getNamedOperand(*MI, AMDGPU::OpName::neg); + const MachineOperand *Src0Mods = getNamedOperand(*MI, + AMDGPU::OpName::src0_modifiers); + const MachineOperand *Src1Mods = getNamedOperand(*MI, + AMDGPU::OpName::src1_modifiers); + const MachineOperand *Src2Mods = getNamedOperand(*MI, + AMDGPU::OpName::src2_modifiers); + + if ((Abs && Abs->getImm()) || (Neg && Neg->getImm()) || + (Src0Mods && Src0Mods->getImm()) || (Src1Mods && Src1Mods->getImm()) || + (Src2Mods && Src2Mods->getImm())) return nullptr; unsigned Reg = MI->getOperand(1).getReg(); @@ -672,6 +679,14 @@ bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const { return AMDGPU::getVOPe32(Opcode) != -1; } +bool SIInstrInfo::hasModifiers(unsigned Opcode) const { + // The src0_modifier operand is present on all instructions + // that have modifiers. + + return AMDGPU::getNamedOperandIdx(Opcode, + AMDGPU::OpName::src0_modifiers) != -1; +} + bool SIInstrInfo::verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const { uint16_t Opcode = MI->getOpcode(); @@ -688,14 +703,20 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI, } // Make sure the register classes are correct - for (unsigned i = 0, e = Desc.getNumOperands(); i != e; ++i) { + for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) { switch (Desc.OpInfo[i].OperandType) { case MCOI::OPERAND_REGISTER: { int RegClass = Desc.OpInfo[i].RegClass; if (!RI.regClassCanUseImmediate(RegClass) && (MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm())) { - ErrInfo = "Expected register, but got immediate"; - return false; + // Handle some special cases: + // Src0 can of VOP1, VOP2, VOPC can be an immediate no matter what + // the register class. + if (i != Src0Idx || (!isVOP1(Opcode) && !isVOP2(Opcode) && + !isVOPC(Opcode))) { + ErrInfo = "Expected register, but got immediate"; + return false; + } } } break; @@ -1423,17 +1444,9 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const { // We are converting these to a BFE, so we need to add the missing // operands for the size and offset. unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16; - Inst->addOperand(Inst->getOperand(1)); - Inst->getOperand(1).ChangeToImmediate(0); - Inst->addOperand(MachineOperand::CreateImm(0)); - Inst->addOperand(MachineOperand::CreateImm(0)); Inst->addOperand(MachineOperand::CreateImm(0)); Inst->addOperand(MachineOperand::CreateImm(Size)); - // XXX - Other pointless operands. There are 4, but it seems you only need - // 3 to not hit an assertion later in MCInstLower. - Inst->addOperand(MachineOperand::CreateImm(0)); - Inst->addOperand(MachineOperand::CreateImm(0)); } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) { // The VALU version adds the second operand to the result, so insert an // extra 0 operand. @@ -1452,16 +1465,9 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const { uint32_t Offset = Imm & 0x3f; // Extract bits [5:0]. uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16]. - Inst->RemoveOperand(2); // Remove old immediate. - Inst->addOperand(Inst->getOperand(1)); - Inst->getOperand(1).ChangeToImmediate(0); - Inst->addOperand(MachineOperand::CreateImm(0)); Inst->addOperand(MachineOperand::CreateImm(Offset)); - Inst->addOperand(MachineOperand::CreateImm(0)); Inst->addOperand(MachineOperand::CreateImm(BitWidth)); - Inst->addOperand(MachineOperand::CreateImm(0)); - Inst->addOperand(MachineOperand::CreateImm(0)); } // Update the destination register class. diff --git a/lib/Target/R600/SIInstrInfo.h b/lib/Target/R600/SIInstrInfo.h index 08e9032e9af..9564d4e9a5e 100644 --- a/lib/Target/R600/SIInstrInfo.h +++ b/lib/Target/R600/SIInstrInfo.h @@ -119,6 +119,9 @@ public: /// This function will return false if you pass it a 32-bit instruction. bool hasVALU32BitEncoding(unsigned Opcode) const; + /// \brief Return true if this instruction has any modifiers. + /// e.g. src[012]_mod, omod, clamp. + bool hasModifiers(unsigned Opcode) const; bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const override; @@ -219,4 +222,11 @@ namespace SIInstrFlags { }; } +namespace SISrcMods { + enum { + NEG = 1 << 0, + ABS = 1 << 1 + }; +} + #endif //SIINSTRINFO_H diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index b0ac20f558d..8cfdf60251f 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -159,6 +159,8 @@ def sopp_brtarget : Operand { let OperandType = "OPERAND_PCREL"; } +include "SIInstrFormats.td" + //===----------------------------------------------------------------------===// // Complex patterns //===----------------------------------------------------------------------===// @@ -167,6 +169,9 @@ def MUBUFAddr32 : ComplexPattern; def MUBUFAddr64 : ComplexPattern; def MUBUFScratch : ComplexPattern; +def VOP3Mods0 : ComplexPattern; +def VOP3Mods : ComplexPattern; + //===----------------------------------------------------------------------===// // SI assembler operands //===----------------------------------------------------------------------===// @@ -176,7 +181,17 @@ def SIOperand { int VCC = 0x6A; } -include "SIInstrFormats.td" +def SRCMODS { + int NONE = 0; +} + +def DSTCLAMP { + int NONE = 0; +} + +def DSTOMOD { + int NONE = 0; +} //===----------------------------------------------------------------------===// // @@ -270,6 +285,195 @@ multiclass SMRD_Helper op, string asm, RegisterClass baseClass, // Vector ALU classes //===----------------------------------------------------------------------===// +// This must always be right before the operand being input modified. +def InputMods : OperandWithDefaultOps { + let PrintMethod = "printOperandAndMods"; +} +def InputModsNoDefault : Operand { + let PrintMethod = "printOperandAndMods"; +} + +class getNumSrcArgs { + int ret = + !if (!eq(Src1.Value, untyped.Value), 1, // VOP1 + !if (!eq(Src2.Value, untyped.Value), 2, // VOP2 + 3)); // VOP3 +} + +// Returns the register class to use for the destination of VOP[123C] +// instructions for the given VT. +class getVALUDstForVT { + RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64); +} + +// Returns the register class to use for source 0 of VOP[12C] +// instructions for the given VT. +class getVOPSrc0ForVT { + RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64); +} + +// Returns the register class to use for source 1 of VOP[12C] for the +// given VT. +class getVOPSrc1ForVT { + RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64); +} + +// Returns the register classes for the source arguments of a VOP[12C] +// instruction for the given SrcVTs. +class getInRC32 SrcVT> { + list ret = [ + getVOPSrc0ForVT.ret, + getVOPSrc1ForVT.ret + ]; +} + +// Returns the register class to use for sources of VOP3 instructions for the +// given VT. +class getVOP3SrcForVT { + RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64); +} + +// Returns the register classes for the source arguments of a VOP3 +// instruction for the given SrcVTs. +class getInRC64 SrcVT> { + list ret = [ + getVOP3SrcForVT.ret, + getVOP3SrcForVT.ret, + getVOP3SrcForVT.ret + ]; +} + +// Returns 1 if the source arguments have modifiers, 0 if they do not. +class hasModifiers { + bit ret = !if(!eq(SrcVT.Value, f32.Value), 1, + !if(!eq(SrcVT.Value, f64.Value), 1, 0)); +} + +// Returns the input arguments for VOP[12C] instructions for the given SrcVT. +class getIns32 { + dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1 + !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2 + (ins))); +} + +// Returns the input arguments for VOP3 instructions for the given SrcVT. +class getIns64 { + + dag ret = + !if (!eq(NumSrcArgs, 1), + !if (!eq(HasModifiers, 1), + // VOP1 with modifiers + (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, + i32imm:$clamp, i32imm:$omod) + /* else */, + // VOP1 without modifiers + (ins Src0RC:$src0) + /* endif */ ), + !if (!eq(NumSrcArgs, 2), + !if (!eq(HasModifiers, 1), + // VOP 2 with modifiers + (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, + InputModsNoDefault:$src1_modifiers, Src1RC:$src1, + i32imm:$clamp, i32imm:$omod) + /* else */, + // VOP2 without modifiers + (ins Src0RC:$src0, Src1RC:$src1) + /* endif */ ) + /* NumSrcArgs == 3 */, + !if (!eq(HasModifiers, 1), + // VOP3 with modifiers + (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, + InputModsNoDefault:$src1_modifiers, Src1RC:$src1, + InputModsNoDefault:$src2_modifiers, Src2RC:$src2, + i32imm:$clamp, i32imm:$omod) + /* else */, + // VOP3 without modifiers + (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2) + /* endif */ ))); +} + +// Returns the assembly string for the inputs and outputs of a VOP[12C] +// instruction. This does not add the _e32 suffix, so it can be reused +// by getAsm64. +class getAsm32 { + string src1 = ", $src1"; + string src2 = ", $src2"; + string ret = " $dst, $src0"# + !if(!eq(NumSrcArgs, 1), "", src1)# + !if(!eq(NumSrcArgs, 3), src2, ""); +} + +// Returns the assembly string for the inputs and outputs of a VOP3 +// instruction. +class getAsm64 { + string src0 = "$src0_modifiers,"; + string src1 = !if(!eq(NumSrcArgs, 1), "", " $src1_modifiers,"); + string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers,", ""); + string ret = + !if(!eq(HasModifiers, 0), + getAsm32.ret, + " $dst, "#src0#src1#src2#" $clamp, $omod"); +} + + +class VOPProfile _ArgVT> { + + field list ArgVT = _ArgVT; + + field ValueType DstVT = ArgVT[0]; + field ValueType Src0VT = ArgVT[1]; + field ValueType Src1VT = ArgVT[2]; + field ValueType Src2VT = ArgVT[3]; + field RegisterClass DstRC = getVALUDstForVT.ret; + field RegisterClass Src0RC32 = getVOPSrc0ForVT.ret; + field RegisterClass Src1RC32 = getVOPSrc1ForVT.ret; + field RegisterClass Src0RC64 = getVOP3SrcForVT.ret; + field RegisterClass Src1RC64 = getVOP3SrcForVT.ret; + field RegisterClass Src2RC64 = getVOP3SrcForVT.ret; + + field int NumSrcArgs = getNumSrcArgs.ret; + field bit HasModifiers = hasModifiers.ret; + + field dag Outs = (outs DstRC:$dst); + + field dag Ins32 = getIns32.ret; + field dag Ins64 = getIns64.ret; + + field string Asm32 = "_e32 "#getAsm32.ret; + field string Asm64 = getAsm64.ret; +} + +def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>; +def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>; +def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>; +def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>; +def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>; +def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>; +def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>; +def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>; +def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>; + +def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>; +def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>; +def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>; +def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>; +def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>; +def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>; +def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> { + let Src0RC32 = VReg_32; +} +def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>; +def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>; + +def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>; +def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>; +def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>; +def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>; + + class VOP { string OpName = opName; } @@ -284,6 +488,17 @@ class SIMCInstr { int Subtarget = subtarget; } +class VOP3DisableFields { + + bits<2> src0_modifiers = !if(HasModifiers, ?, 0); + bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0); + bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0); + bits<2> omod = !if(HasModifiers, ?, 0); + bits<1> clamp = !if(HasModifiers, ?, 0); + bits<9> src1 = !if(HasSrc1, ?, 0); + bits<9> src2 = !if(HasSrc2, ?, 0); +} + class VOP3_Pseudo pattern, string opName> : VOP3Common , VOP , @@ -296,212 +511,259 @@ class VOP3_Real_si op, dag outs, dag ins, string asm, string opName> : SIMCInstr; multiclass VOP3_m op, dag outs, dag ins, string asm, list pattern, - string opName> { + string opName, int NumSrcArgs, bit HasMods = 1> { def "" : VOP3_Pseudo ; - def _si : VOP3_Real_si ; + def _si : VOP3_Real_si , + VOP3DisableFields; } multiclass VOP3_1_m op, dag outs, dag ins, string asm, - list pattern, string opName> { + list pattern, string opName, bit HasMods = 1> { def "" : VOP3_Pseudo ; - let src1 = 0, src1_modifiers = 0, src2 = 0, src2_modifiers = 0 in { - - def _si : VOP3_Real_si < - {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - outs, ins, asm, opName - >; - - } // src1 = 0, src1_modifiers = 0, src2 = 0, src2_modifiers = 0 + def _si : VOP3_Real_si < + {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + outs, ins, asm, opName>, + VOP3DisableFields<0, 0, HasMods>; } -multiclass VOP3_2_m op, dag outs, dag ins, string asm, - list pattern, string opName, string revOp> { +multiclass VOP3_2_m op, dag outs, dag ins, string asm, + list pattern, string opName, string revOp, + bit HasMods = 1, bit UseFullOp = 0> { - def "" : VOP3_Pseudo ; - - let src2 = 0, src2_modifiers = 0 in { - - def _si : VOP3_Real_si < - {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - outs, ins, asm, opName>, - VOP2_REV; + def "" : VOP3_Pseudo , + VOP2_REV; - } // src2 = 0, src2_modifiers = 0 + def _si : VOP3_Real_si , + VOP2_REV, + VOP3DisableFields<1, 0, HasMods>; } -// This must always be right before the operand being input modified. -def InputMods : OperandWithDefaultOps { - let PrintMethod = "printOperandAndMods"; +multiclass VOP3b_2_m op, dag outs, dag ins, string asm, + list pattern, string opName, string revOp, + bit HasMods = 1, bit UseFullOp = 0> { + def "" : VOP3_Pseudo , + VOP2_REV; + + // The VOP2 variant puts the carry out into VCC, the VOP3 variant + // can write it into any SGPR. We currently don't use the carry out, + // so for now hardcode it to VCC as well. + let sdst = SIOperand.VCC, Defs = [VCC] in { + def _si : VOP3b , + VOP3DisableFields<1, 0, HasMods>, + SIMCInstr, + VOP2_REV; + } // End sdst = SIOperand.VCC, Defs = [VCC] } -multiclass VOP1_Helper op, RegisterClass drc, RegisterClass src, - string opName, list pattern> { +multiclass VOP3_C_m op, dag outs, dag ins, string asm, + list pattern, string opName, + bit HasMods, bit defExec> { - def _e32 : VOP1 < - op, (outs drc:$dst), (ins src:$src0), - opName#"_e32 $dst, $src0", pattern - >, VOP ; + def "" : VOP3_Pseudo ; - defm _e64 : VOP3_1_m < - op, - (outs drc:$dst), - (ins InputMods:$src0_modifiers, src:$src0, i32imm:$clamp, i32imm:$omod), - opName#"_e64 $dst, $src0_modifiers, $clamp, $omod", [], opName>; + def _si : VOP3_Real_si < + {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + outs, ins, asm, opName>, + VOP3DisableFields<1, 0, HasMods> { + let Defs = !if(defExec, [EXEC], []); + } } -multiclass VOP1_32 op, string opName, list pattern> - : VOP1_Helper ; +multiclass VOP1_Helper op, string opName, dag outs, + dag ins32, string asm32, list pat32, + dag ins64, string asm64, list pat64, + bit HasMods> { -multiclass VOP1_64 op, string opName, list pattern> - : VOP1_Helper ; + def _e32 : VOP1 , VOP; -multiclass VOP1_32_64 op, string opName, list pattern> - : VOP1_Helper ; + defm _e64 : VOP3_1_m ; +} -multiclass VOP1_64_32 op, string opName, list pattern> - : VOP1_Helper ; +multiclass VOP1Inst op, string opName, VOPProfile P, + SDPatternOperator node = null_frag> : VOP1_Helper < + op, opName, P.Outs, + P.Ins32, P.Asm32, [], + P.Ins64, P.Asm64, + !if(P.HasModifiers, + [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, + i32:$src0_modifiers, i32:$clamp, i32:$omod))))], + [(set P.DstVT:$dst, (node P.Src0VT:$src0))]), + P.HasModifiers +>; -multiclass VOP2_Helper op, RegisterClass vrc, RegisterClass arc, - string opName, list pattern, string revOp> { - def _e32 : VOP2 < - op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), - opName#"_e32 $dst, $src0, $src1", pattern - >, VOP , VOP2_REV; +class VOP2_e32 op, string opName, dag outs, dag ins, string asm, + list pattern, string revOp> : + VOP2 , + VOP , + VOP2_REV; + +multiclass VOP2_Helper op, string opName, dag outs, + dag ins32, string asm32, list pat32, + dag ins64, string asm64, list pat64, + string revOp, bit HasMods> { + def _e32 : VOP2_e32 ; defm _e64 : VOP3_2_m < - op, - (outs vrc:$dst), - (ins InputMods:$src0_modifiers, arc:$src0, - InputMods:$src1_modifiers, arc:$src1, - i32imm:$clamp, i32imm:$omod), - opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod", [], - opName, revOp>; + {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods + >; } -multiclass VOP2_32 op, string opName, list pattern, - string revOp = opName> - : VOP2_Helper ; - -multiclass VOP2_64 op, string opName, list pattern, - string revOp = opName> - : VOP2_Helper ; +multiclass VOP2Inst op, string opName, VOPProfile P, + SDPatternOperator node = null_frag, + string revOp = opName> : VOP2_Helper < + op, opName, P.Outs, + P.Ins32, P.Asm32, [], + P.Ins64, P.Asm64, + !if(P.HasModifiers, + [(set P.DstVT:$dst, + (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, + i32:$clamp, i32:$omod)), + (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], + [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), + revOp, P.HasModifiers +>; -multiclass VOP2b_32 op, string opName, list pattern, - RegisterClass src0_rc, string revOp = opName> { +multiclass VOP2b_Helper op, string opName, dag outs, + dag ins32, string asm32, list pat32, + dag ins64, string asm64, list pat64, + string revOp, bit HasMods> { - def _e32 : VOP2 < - op, (outs VReg_32:$dst), (ins src0_rc:$src0, VReg_32:$src1), - opName#"_e32 $dst, $src0, $src1", pattern - >, VOP , VOP2_REV; + def _e32 : VOP2_e32 ; - def _e64 : VOP3b < + defm _e64 : VOP3b_2_m < {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - (outs VReg_32:$dst), - (ins InputMods: $src0_modifiers, VSrc_32:$src0, - InputMods:$src1_modifiers, VSrc_32:$src1, - i32imm:$clamp, i32imm:$omod), - opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod", [] - >, VOP , VOP2_REV { - let src2 = 0; - let src2_modifiers = 0; - /* the VOP2 variant puts the carry out into VCC, the VOP3 variant - can write it into any SGPR. We currently don't use the carry out, - so for now hardcode it to VCC as well */ - let sdst = SIOperand.VCC; - } + outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods + >; } -multiclass VOPC_Helper op, RegisterClass vrc, RegisterClass arc, - string opName, ValueType vt, PatLeaf cond, bit defExec = 0> { - def _e32 : VOPC < - op, (ins arc:$src0, vrc:$src1), - opName#"_e32 $dst, $src0, $src1", [] - >, VOP { - let Defs = !if(defExec, [EXEC], []); - } +multiclass VOP2bInst op, string opName, VOPProfile P, + SDPatternOperator node = null_frag, + string revOp = opName> : VOP2b_Helper < + op, opName, P.Outs, + P.Ins32, P.Asm32, [], + P.Ins64, P.Asm64, + !if(P.HasModifiers, + [(set P.DstVT:$dst, + (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, + i32:$clamp, i32:$omod)), + (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], + [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), + revOp, P.HasModifiers +>; - def _e64 : VOP3 < - {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - (outs SReg_64:$dst), - (ins InputMods:$src0_modifiers, arc:$src0, - InputMods:$src1_modifiers, arc:$src1, - InstFlag:$clamp, InstFlag:$omod), - opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod", - !if(!eq(!cast(cond), "COND_NULL"), [], - [(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), arc:$src1, cond)))] - ) - >, VOP { - let Defs = !if(defExec, [EXEC], []); - let src2 = 0; - let src2_modifiers = 0; +multiclass VOPC_Helper op, string opName, + dag ins32, string asm32, list pat32, + dag out64, dag ins64, string asm64, list pat64, + bit HasMods, bit DefExec> { + def _e32 : VOPC , VOP { + let Defs = !if(DefExec, [EXEC], []); } + + defm _e64 : VOP3_C_m ; } -multiclass VOPC_32 op, string opName, - ValueType vt = untyped, PatLeaf cond = COND_NULL> - : VOPC_Helper ; +multiclass VOPCInst op, string opName, + VOPProfile P, PatLeaf cond = COND_NULL, + bit DefExec = 0> : VOPC_Helper < + op, opName, + P.Ins32, P.Asm32, [], + (outs SReg_64:$dst), P.Ins64, P.Asm64, + !if(P.HasModifiers, + [(set i1:$dst, + (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, + i32:$clamp, i32:$omod)), + (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), + cond))], + [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]), + P.HasModifiers, DefExec +>; -multiclass VOPC_64 op, string opName, - ValueType vt = untyped, PatLeaf cond = COND_NULL> - : VOPC_Helper ; +multiclass VOPC_F32 op, string opName, PatLeaf cond = COND_NULL> : + VOPCInst ; -multiclass VOPCX_32 op, string opName, - ValueType vt = untyped, PatLeaf cond = COND_NULL> - : VOPC_Helper ; +multiclass VOPC_F64 op, string opName, PatLeaf cond = COND_NULL> : + VOPCInst ; -multiclass VOPCX_64 op, string opName, - ValueType vt = untyped, PatLeaf cond = COND_NULL> - : VOPC_Helper ; +multiclass VOPC_I32 op, string opName, PatLeaf cond = COND_NULL> : + VOPCInst ; -multiclass VOP3_32 op, string opName, list pattern> : VOP3_m < - op, (outs VReg_32:$dst), - (ins InputMods: $src0_modifiers, VSrc_32:$src0, InputMods:$src1_modifiers, - VSrc_32:$src1, InputMods:$src2_modifiers, VSrc_32:$src2, - InstFlag:$clamp, InstFlag:$omod), - opName#" $dst, $src0_modifiers, $src1, $src2, $clamp, $omod", pattern, opName ->; +multiclass VOPC_I64 op, string opName, PatLeaf cond = COND_NULL> : + VOPCInst ; -class VOP3_64_32 op, string opName, list pattern> : VOP3 < - op, (outs VReg_64:$dst), - (ins VSrc_64:$src0, VSrc_32:$src1), - opName#" $dst, $src0, $src1", pattern ->, VOP { - let src2 = 0; - let src2_modifiers = 0; - let src0_modifiers = 0; - let clamp = 0; - let omod = 0; -} +multiclass VOPCX op, string opName, VOPProfile P, + PatLeaf cond = COND_NULL> + : VOPCInst ; -class VOP3_64 op, string opName, list pattern> : VOP3 < - op, (outs VReg_64:$dst), - (ins InputMods:$src0_modifiers, VSrc_64:$src0, - InputMods:$src1_modifiers, VSrc_64:$src1, - InputMods:$src2_modifiers, VSrc_64:$src2, - InstFlag:$clamp, InstFlag:$omod), - opName#" $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers, $clamp, $omod", pattern ->, VOP ; +multiclass VOPCX_F32 op, string opName, PatLeaf cond = COND_NULL> : + VOPCX ; +multiclass VOPCX_F64 op, string opName, PatLeaf cond = COND_NULL> : + VOPCX ; -class VOP3b_Helper op, RegisterClass vrc, RegisterClass arc, - string opName, list pattern> : VOP3 < +multiclass VOPCX_I32 op, string opName, PatLeaf cond = COND_NULL> : + VOPCX ; + +multiclass VOPCX_I64 op, string opName, PatLeaf cond = COND_NULL> : + VOPCX ; + +multiclass VOP3_Helper op, string opName, dag outs, dag ins, string asm, + list pat, int NumSrcArgs, bit HasMods> : VOP3_m < + op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods +>; + +multiclass VOP3Inst op, string opName, VOPProfile P, + SDPatternOperator node = null_frag> : VOP3_Helper < + op, opName, P.Outs, P.Ins64, P.Asm64, + !if(!eq(P.NumSrcArgs, 3), + !if(P.HasModifiers, + [(set P.DstVT:$dst, + (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, + i32:$clamp, i32:$omod)), + (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), + (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))], + [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1, + P.Src2VT:$src2))]), + !if(!eq(P.NumSrcArgs, 2), + !if(P.HasModifiers, + [(set P.DstVT:$dst, + (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, + i32:$clamp, i32:$omod)), + (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], + [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]) + /* P.NumSrcArgs == 1 */, + !if(P.HasModifiers, + [(set P.DstVT:$dst, + (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, + i32:$clamp, i32:$omod))))], + [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))), + P.NumSrcArgs, P.HasModifiers +>; + +multiclass VOP3b_Helper op, RegisterClass vrc, RegisterClass arc, + string opName, list pattern> : + VOP3b_2_m < op, (outs vrc:$dst0, SReg_64:$dst1), (ins arc:$src0, arc:$src1, arc:$src2, InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), - opName#" $dst0, $dst1, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern ->, VOP ; - + opName#" $dst0, $dst1, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern, + opName, opName, 1, 1 +>; -class VOP3b_64 op, string opName, list pattern> : +multiclass VOP3b_64 op, string opName, list pattern> : VOP3b_Helper ; -class VOP3b_32 op, string opName, list pattern> : +multiclass VOP3b_32 op, string opName, list pattern> : VOP3b_Helper ; //===----------------------------------------------------------------------===// diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 1434234da48..5ddc8ddafa1 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -464,256 +464,256 @@ let Uses = [EXEC] in { let isCompare = 1 in { -defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">; -defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>; -defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>; -defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>; -defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>; -defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">; -defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>; -defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>; -defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>; -defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">; -defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">; -defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">; -defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">; -defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>; -defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">; -defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">; +defm V_CMP_F_F32 : VOPC_F32 <0x00000000, "V_CMP_F_F32">; +defm V_CMP_LT_F32 : VOPC_F32 <0x00000001, "V_CMP_LT_F32", COND_OLT>; +defm V_CMP_EQ_F32 : VOPC_F32 <0x00000002, "V_CMP_EQ_F32", COND_OEQ>; +defm V_CMP_LE_F32 : VOPC_F32 <0x00000003, "V_CMP_LE_F32", COND_OLE>; +defm V_CMP_GT_F32 : VOPC_F32 <0x00000004, "V_CMP_GT_F32", COND_OGT>; +defm V_CMP_LG_F32 : VOPC_F32 <0x00000005, "V_CMP_LG_F32">; +defm V_CMP_GE_F32 : VOPC_F32 <0x00000006, "V_CMP_GE_F32", COND_OGE>; +defm V_CMP_O_F32 : VOPC_F32 <0x00000007, "V_CMP_O_F32", COND_O>; +defm V_CMP_U_F32 : VOPC_F32 <0x00000008, "V_CMP_U_F32", COND_UO>; +defm V_CMP_NGE_F32 : VOPC_F32 <0x00000009, "V_CMP_NGE_F32">; +defm V_CMP_NLG_F32 : VOPC_F32 <0x0000000a, "V_CMP_NLG_F32">; +defm V_CMP_NGT_F32 : VOPC_F32 <0x0000000b, "V_CMP_NGT_F32">; +defm V_CMP_NLE_F32 : VOPC_F32 <0x0000000c, "V_CMP_NLE_F32">; +defm V_CMP_NEQ_F32 : VOPC_F32 <0x0000000d, "V_CMP_NEQ_F32", COND_UNE>; +defm V_CMP_NLT_F32 : VOPC_F32 <0x0000000e, "V_CMP_NLT_F32">; +defm V_CMP_TRU_F32 : VOPC_F32 <0x0000000f, "V_CMP_TRU_F32">; let hasSideEffects = 1 in { -defm V_CMPX_F_F32 : VOPCX_32 <0x00000010, "V_CMPX_F_F32">; -defm V_CMPX_LT_F32 : VOPCX_32 <0x00000011, "V_CMPX_LT_F32">; -defm V_CMPX_EQ_F32 : VOPCX_32 <0x00000012, "V_CMPX_EQ_F32">; -defm V_CMPX_LE_F32 : VOPCX_32 <0x00000013, "V_CMPX_LE_F32">; -defm V_CMPX_GT_F32 : VOPCX_32 <0x00000014, "V_CMPX_GT_F32">; -defm V_CMPX_LG_F32 : VOPCX_32 <0x00000015, "V_CMPX_LG_F32">; -defm V_CMPX_GE_F32 : VOPCX_32 <0x00000016, "V_CMPX_GE_F32">; -defm V_CMPX_O_F32 : VOPCX_32 <0x00000017, "V_CMPX_O_F32">; -defm V_CMPX_U_F32 : VOPCX_32 <0x00000018, "V_CMPX_U_F32">; -defm V_CMPX_NGE_F32 : VOPCX_32 <0x00000019, "V_CMPX_NGE_F32">; -defm V_CMPX_NLG_F32 : VOPCX_32 <0x0000001a, "V_CMPX_NLG_F32">; -defm V_CMPX_NGT_F32 : VOPCX_32 <0x0000001b, "V_CMPX_NGT_F32">; -defm V_CMPX_NLE_F32 : VOPCX_32 <0x0000001c, "V_CMPX_NLE_F32">; -defm V_CMPX_NEQ_F32 : VOPCX_32 <0x0000001d, "V_CMPX_NEQ_F32">; -defm V_CMPX_NLT_F32 : VOPCX_32 <0x0000001e, "V_CMPX_NLT_F32">; -defm V_CMPX_TRU_F32 : VOPCX_32 <0x0000001f, "V_CMPX_TRU_F32">; +defm V_CMPX_F_F32 : VOPCX_F32 <0x00000010, "V_CMPX_F_F32">; +defm V_CMPX_LT_F32 : VOPCX_F32 <0x00000011, "V_CMPX_LT_F32">; +defm V_CMPX_EQ_F32 : VOPCX_F32 <0x00000012, "V_CMPX_EQ_F32">; +defm V_CMPX_LE_F32 : VOPCX_F32 <0x00000013, "V_CMPX_LE_F32">; +defm V_CMPX_GT_F32 : VOPCX_F32 <0x00000014, "V_CMPX_GT_F32">; +defm V_CMPX_LG_F32 : VOPCX_F32 <0x00000015, "V_CMPX_LG_F32">; +defm V_CMPX_GE_F32 : VOPCX_F32 <0x00000016, "V_CMPX_GE_F32">; +defm V_CMPX_O_F32 : VOPCX_F32 <0x00000017, "V_CMPX_O_F32">; +defm V_CMPX_U_F32 : VOPCX_F32 <0x00000018, "V_CMPX_U_F32">; +defm V_CMPX_NGE_F32 : VOPCX_F32 <0x00000019, "V_CMPX_NGE_F32">; +defm V_CMPX_NLG_F32 : VOPCX_F32 <0x0000001a, "V_CMPX_NLG_F32">; +defm V_CMPX_NGT_F32 : VOPCX_F32 <0x0000001b, "V_CMPX_NGT_F32">; +defm V_CMPX_NLE_F32 : VOPCX_F32 <0x0000001c, "V_CMPX_NLE_F32">; +defm V_CMPX_NEQ_F32 : VOPCX_F32 <0x0000001d, "V_CMPX_NEQ_F32">; +defm V_CMPX_NLT_F32 : VOPCX_F32 <0x0000001e, "V_CMPX_NLT_F32">; +defm V_CMPX_TRU_F32 : VOPCX_F32 <0x0000001f, "V_CMPX_TRU_F32">; } // End hasSideEffects = 1 -defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">; -defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>; -defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>; -defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>; -defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>; -defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">; -defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>; -defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>; -defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>; -defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">; -defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">; -defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">; -defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">; -defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>; -defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">; -defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">; +defm V_CMP_F_F64 : VOPC_F64 <0x00000020, "V_CMP_F_F64">; +defm V_CMP_LT_F64 : VOPC_F64 <0x00000021, "V_CMP_LT_F64", COND_OLT>; +defm V_CMP_EQ_F64 : VOPC_F64 <0x00000022, "V_CMP_EQ_F64", COND_OEQ>; +defm V_CMP_LE_F64 : VOPC_F64 <0x00000023, "V_CMP_LE_F64", COND_OLE>; +defm V_CMP_GT_F64 : VOPC_F64 <0x00000024, "V_CMP_GT_F64", COND_OGT>; +defm V_CMP_LG_F64 : VOPC_F64 <0x00000025, "V_CMP_LG_F64">; +defm V_CMP_GE_F64 : VOPC_F64 <0x00000026, "V_CMP_GE_F64", COND_OGE>; +defm V_CMP_O_F64 : VOPC_F64 <0x00000027, "V_CMP_O_F64", COND_O>; +defm V_CMP_U_F64 : VOPC_F64 <0x00000028, "V_CMP_U_F64", COND_UO>; +defm V_CMP_NGE_F64 : VOPC_F64 <0x00000029, "V_CMP_NGE_F64">; +defm V_CMP_NLG_F64 : VOPC_F64 <0x0000002a, "V_CMP_NLG_F64">; +defm V_CMP_NGT_F64 : VOPC_F64 <0x0000002b, "V_CMP_NGT_F64">; +defm V_CMP_NLE_F64 : VOPC_F64 <0x0000002c, "V_CMP_NLE_F64">; +defm V_CMP_NEQ_F64 : VOPC_F64 <0x0000002d, "V_CMP_NEQ_F64", COND_UNE>; +defm V_CMP_NLT_F64 : VOPC_F64 <0x0000002e, "V_CMP_NLT_F64">; +defm V_CMP_TRU_F64 : VOPC_F64 <0x0000002f, "V_CMP_TRU_F64">; let hasSideEffects = 1 in { -defm V_CMPX_F_F64 : VOPCX_64 <0x00000030, "V_CMPX_F_F64">; -defm V_CMPX_LT_F64 : VOPCX_64 <0x00000031, "V_CMPX_LT_F64">; -defm V_CMPX_EQ_F64 : VOPCX_64 <0x00000032, "V_CMPX_EQ_F64">; -defm V_CMPX_LE_F64 : VOPCX_64 <0x00000033, "V_CMPX_LE_F64">; -defm V_CMPX_GT_F64 : VOPCX_64 <0x00000034, "V_CMPX_GT_F64">; -defm V_CMPX_LG_F64 : VOPCX_64 <0x00000035, "V_CMPX_LG_F64">; -defm V_CMPX_GE_F64 : VOPCX_64 <0x00000036, "V_CMPX_GE_F64">; -defm V_CMPX_O_F64 : VOPCX_64 <0x00000037, "V_CMPX_O_F64">; -defm V_CMPX_U_F64 : VOPCX_64 <0x00000038, "V_CMPX_U_F64">; -defm V_CMPX_NGE_F64 : VOPCX_64 <0x00000039, "V_CMPX_NGE_F64">; -defm V_CMPX_NLG_F64 : VOPCX_64 <0x0000003a, "V_CMPX_NLG_F64">; -defm V_CMPX_NGT_F64 : VOPCX_64 <0x0000003b, "V_CMPX_NGT_F64">; -defm V_CMPX_NLE_F64 : VOPCX_64 <0x0000003c, "V_CMPX_NLE_F64">; -defm V_CMPX_NEQ_F64 : VOPCX_64 <0x0000003d, "V_CMPX_NEQ_F64">; -defm V_CMPX_NLT_F64 : VOPCX_64 <0x0000003e, "V_CMPX_NLT_F64">; -defm V_CMPX_TRU_F64 : VOPCX_64 <0x0000003f, "V_CMPX_TRU_F64">; +defm V_CMPX_F_F64 : VOPCX_F64 <0x00000030, "V_CMPX_F_F64">; +defm V_CMPX_LT_F64 : VOPCX_F64 <0x00000031, "V_CMPX_LT_F64">; +defm V_CMPX_EQ_F64 : VOPCX_F64 <0x00000032, "V_CMPX_EQ_F64">; +defm V_CMPX_LE_F64 : VOPCX_F64 <0x00000033, "V_CMPX_LE_F64">; +defm V_CMPX_GT_F64 : VOPCX_F64 <0x00000034, "V_CMPX_GT_F64">; +defm V_CMPX_LG_F64 : VOPCX_F64 <0x00000035, "V_CMPX_LG_F64">; +defm V_CMPX_GE_F64 : VOPCX_F64 <0x00000036, "V_CMPX_GE_F64">; +defm V_CMPX_O_F64 : VOPCX_F64 <0x00000037, "V_CMPX_O_F64">; +defm V_CMPX_U_F64 : VOPCX_F64 <0x00000038, "V_CMPX_U_F64">; +defm V_CMPX_NGE_F64 : VOPCX_F64 <0x00000039, "V_CMPX_NGE_F64">; +defm V_CMPX_NLG_F64 : VOPCX_F64 <0x0000003a, "V_CMPX_NLG_F64">; +defm V_CMPX_NGT_F64 : VOPCX_F64 <0x0000003b, "V_CMPX_NGT_F64">; +defm V_CMPX_NLE_F64 : VOPCX_F64 <0x0000003c, "V_CMPX_NLE_F64">; +defm V_CMPX_NEQ_F64 : VOPCX_F64 <0x0000003d, "V_CMPX_NEQ_F64">; +defm V_CMPX_NLT_F64 : VOPCX_F64 <0x0000003e, "V_CMPX_NLT_F64">; +defm V_CMPX_TRU_F64 : VOPCX_F64 <0x0000003f, "V_CMPX_TRU_F64">; } // End hasSideEffects = 1 -defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">; -defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">; -defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">; -defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">; -defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">; -defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">; -defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">; -defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">; -defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">; -defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">; -defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">; -defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">; -defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">; -defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">; -defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">; -defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">; +defm V_CMPS_F_F32 : VOPC_F32 <0x00000040, "V_CMPS_F_F32">; +defm V_CMPS_LT_F32 : VOPC_F32 <0x00000041, "V_CMPS_LT_F32">; +defm V_CMPS_EQ_F32 : VOPC_F32 <0x00000042, "V_CMPS_EQ_F32">; +defm V_CMPS_LE_F32 : VOPC_F32 <0x00000043, "V_CMPS_LE_F32">; +defm V_CMPS_GT_F32 : VOPC_F32 <0x00000044, "V_CMPS_GT_F32">; +defm V_CMPS_LG_F32 : VOPC_F32 <0x00000045, "V_CMPS_LG_F32">; +defm V_CMPS_GE_F32 : VOPC_F32 <0x00000046, "V_CMPS_GE_F32">; +defm V_CMPS_O_F32 : VOPC_F32 <0x00000047, "V_CMPS_O_F32">; +defm V_CMPS_U_F32 : VOPC_F32 <0x00000048, "V_CMPS_U_F32">; +defm V_CMPS_NGE_F32 : VOPC_F32 <0x00000049, "V_CMPS_NGE_F32">; +defm V_CMPS_NLG_F32 : VOPC_F32 <0x0000004a, "V_CMPS_NLG_F32">; +defm V_CMPS_NGT_F32 : VOPC_F32 <0x0000004b, "V_CMPS_NGT_F32">; +defm V_CMPS_NLE_F32 : VOPC_F32 <0x0000004c, "V_CMPS_NLE_F32">; +defm V_CMPS_NEQ_F32 : VOPC_F32 <0x0000004d, "V_CMPS_NEQ_F32">; +defm V_CMPS_NLT_F32 : VOPC_F32 <0x0000004e, "V_CMPS_NLT_F32">; +defm V_CMPS_TRU_F32 : VOPC_F32 <0x0000004f, "V_CMPS_TRU_F32">; let hasSideEffects = 1 in { -defm V_CMPSX_F_F32 : VOPCX_32 <0x00000050, "V_CMPSX_F_F32">; -defm V_CMPSX_LT_F32 : VOPCX_32 <0x00000051, "V_CMPSX_LT_F32">; -defm V_CMPSX_EQ_F32 : VOPCX_32 <0x00000052, "V_CMPSX_EQ_F32">; -defm V_CMPSX_LE_F32 : VOPCX_32 <0x00000053, "V_CMPSX_LE_F32">; -defm V_CMPSX_GT_F32 : VOPCX_32 <0x00000054, "V_CMPSX_GT_F32">; -defm V_CMPSX_LG_F32 : VOPCX_32 <0x00000055, "V_CMPSX_LG_F32">; -defm V_CMPSX_GE_F32 : VOPCX_32 <0x00000056, "V_CMPSX_GE_F32">; -defm V_CMPSX_O_F32 : VOPCX_32 <0x00000057, "V_CMPSX_O_F32">; -defm V_CMPSX_U_F32 : VOPCX_32 <0x00000058, "V_CMPSX_U_F32">; -defm V_CMPSX_NGE_F32 : VOPCX_32 <0x00000059, "V_CMPSX_NGE_F32">; -defm V_CMPSX_NLG_F32 : VOPCX_32 <0x0000005a, "V_CMPSX_NLG_F32">; -defm V_CMPSX_NGT_F32 : VOPCX_32 <0x0000005b, "V_CMPSX_NGT_F32">; -defm V_CMPSX_NLE_F32 : VOPCX_32 <0x0000005c, "V_CMPSX_NLE_F32">; -defm V_CMPSX_NEQ_F32 : VOPCX_32 <0x0000005d, "V_CMPSX_NEQ_F32">; -defm V_CMPSX_NLT_F32 : VOPCX_32 <0x0000005e, "V_CMPSX_NLT_F32">; -defm V_CMPSX_TRU_F32 : VOPCX_32 <0x0000005f, "V_CMPSX_TRU_F32">; +defm V_CMPSX_F_F32 : VOPCX_F32 <0x00000050, "V_CMPSX_F_F32">; +defm V_CMPSX_LT_F32 : VOPCX_F32 <0x00000051, "V_CMPSX_LT_F32">; +defm V_CMPSX_EQ_F32 : VOPCX_F32 <0x00000052, "V_CMPSX_EQ_F32">; +defm V_CMPSX_LE_F32 : VOPCX_F32 <0x00000053, "V_CMPSX_LE_F32">; +defm V_CMPSX_GT_F32 : VOPCX_F32 <0x00000054, "V_CMPSX_GT_F32">; +defm V_CMPSX_LG_F32 : VOPCX_F32 <0x00000055, "V_CMPSX_LG_F32">; +defm V_CMPSX_GE_F32 : VOPCX_F32 <0x00000056, "V_CMPSX_GE_F32">; +defm V_CMPSX_O_F32 : VOPCX_F32 <0x00000057, "V_CMPSX_O_F32">; +defm V_CMPSX_U_F32 : VOPCX_F32 <0x00000058, "V_CMPSX_U_F32">; +defm V_CMPSX_NGE_F32 : VOPCX_F32 <0x00000059, "V_CMPSX_NGE_F32">; +defm V_CMPSX_NLG_F32 : VOPCX_F32 <0x0000005a, "V_CMPSX_NLG_F32">; +defm V_CMPSX_NGT_F32 : VOPCX_F32 <0x0000005b, "V_CMPSX_NGT_F32">; +defm V_CMPSX_NLE_F32 : VOPCX_F32 <0x0000005c, "V_CMPSX_NLE_F32">; +defm V_CMPSX_NEQ_F32 : VOPCX_F32 <0x0000005d, "V_CMPSX_NEQ_F32">; +defm V_CMPSX_NLT_F32 : VOPCX_F32 <0x0000005e, "V_CMPSX_NLT_F32">; +defm V_CMPSX_TRU_F32 : VOPCX_F32 <0x0000005f, "V_CMPSX_TRU_F32">; } // End hasSideEffects = 1 -defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">; -defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">; -defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">; -defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">; -defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">; -defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">; -defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">; -defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">; -defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">; -defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">; -defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">; -defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">; -defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">; -defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">; -defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">; -defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">; +defm V_CMPS_F_F64 : VOPC_F64 <0x00000060, "V_CMPS_F_F64">; +defm V_CMPS_LT_F64 : VOPC_F64 <0x00000061, "V_CMPS_LT_F64">; +defm V_CMPS_EQ_F64 : VOPC_F64 <0x00000062, "V_CMPS_EQ_F64">; +defm V_CMPS_LE_F64 : VOPC_F64 <0x00000063, "V_CMPS_LE_F64">; +defm V_CMPS_GT_F64 : VOPC_F64 <0x00000064, "V_CMPS_GT_F64">; +defm V_CMPS_LG_F64 : VOPC_F64 <0x00000065, "V_CMPS_LG_F64">; +defm V_CMPS_GE_F64 : VOPC_F64 <0x00000066, "V_CMPS_GE_F64">; +defm V_CMPS_O_F64 : VOPC_F64 <0x00000067, "V_CMPS_O_F64">; +defm V_CMPS_U_F64 : VOPC_F64 <0x00000068, "V_CMPS_U_F64">; +defm V_CMPS_NGE_F64 : VOPC_F64 <0x00000069, "V_CMPS_NGE_F64">; +defm V_CMPS_NLG_F64 : VOPC_F64 <0x0000006a, "V_CMPS_NLG_F64">; +defm V_CMPS_NGT_F64 : VOPC_F64 <0x0000006b, "V_CMPS_NGT_F64">; +defm V_CMPS_NLE_F64 : VOPC_F64 <0x0000006c, "V_CMPS_NLE_F64">; +defm V_CMPS_NEQ_F64 : VOPC_F64 <0x0000006d, "V_CMPS_NEQ_F64">; +defm V_CMPS_NLT_F64 : VOPC_F64 <0x0000006e, "V_CMPS_NLT_F64">; +defm V_CMPS_TRU_F64 : VOPC_F64 <0x0000006f, "V_CMPS_TRU_F64">; let hasSideEffects = 1, Defs = [EXEC] in { -defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">; -defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">; -defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">; -defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">; -defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">; -defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">; -defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">; -defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">; -defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">; -defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">; -defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">; -defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">; -defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">; -defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">; -defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">; -defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">; +defm V_CMPSX_F_F64 : VOPC_F64 <0x00000070, "V_CMPSX_F_F64">; +defm V_CMPSX_LT_F64 : VOPC_F64 <0x00000071, "V_CMPSX_LT_F64">; +defm V_CMPSX_EQ_F64 : VOPC_F64 <0x00000072, "V_CMPSX_EQ_F64">; +defm V_CMPSX_LE_F64 : VOPC_F64 <0x00000073, "V_CMPSX_LE_F64">; +defm V_CMPSX_GT_F64 : VOPC_F64 <0x00000074, "V_CMPSX_GT_F64">; +defm V_CMPSX_LG_F64 : VOPC_F64 <0x00000075, "V_CMPSX_LG_F64">; +defm V_CMPSX_GE_F64 : VOPC_F64 <0x00000076, "V_CMPSX_GE_F64">; +defm V_CMPSX_O_F64 : VOPC_F64 <0x00000077, "V_CMPSX_O_F64">; +defm V_CMPSX_U_F64 : VOPC_F64 <0x00000078, "V_CMPSX_U_F64">; +defm V_CMPSX_NGE_F64 : VOPC_F64 <0x00000079, "V_CMPSX_NGE_F64">; +defm V_CMPSX_NLG_F64 : VOPC_F64 <0x0000007a, "V_CMPSX_NLG_F64">; +defm V_CMPSX_NGT_F64 : VOPC_F64 <0x0000007b, "V_CMPSX_NGT_F64">; +defm V_CMPSX_NLE_F64 : VOPC_F64 <0x0000007c, "V_CMPSX_NLE_F64">; +defm V_CMPSX_NEQ_F64 : VOPC_F64 <0x0000007d, "V_CMPSX_NEQ_F64">; +defm V_CMPSX_NLT_F64 : VOPC_F64 <0x0000007e, "V_CMPSX_NLT_F64">; +defm V_CMPSX_TRU_F64 : VOPC_F64 <0x0000007f, "V_CMPSX_TRU_F64">; } // End hasSideEffects = 1, Defs = [EXEC] -defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">; -defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>; -defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>; -defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>; -defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>; -defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>; -defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>; -defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">; +defm V_CMP_F_I32 : VOPC_I32 <0x00000080, "V_CMP_F_I32">; +defm V_CMP_LT_I32 : VOPC_I32 <0x00000081, "V_CMP_LT_I32", COND_SLT>; +defm V_CMP_EQ_I32 : VOPC_I32 <0x00000082, "V_CMP_EQ_I32", COND_EQ>; +defm V_CMP_LE_I32 : VOPC_I32 <0x00000083, "V_CMP_LE_I32", COND_SLE>; +defm V_CMP_GT_I32 : VOPC_I32 <0x00000084, "V_CMP_GT_I32", COND_SGT>; +defm V_CMP_NE_I32 : VOPC_I32 <0x00000085, "V_CMP_NE_I32", COND_NE>; +defm V_CMP_GE_I32 : VOPC_I32 <0x00000086, "V_CMP_GE_I32", COND_SGE>; +defm V_CMP_T_I32 : VOPC_I32 <0x00000087, "V_CMP_T_I32">; let hasSideEffects = 1 in { -defm V_CMPX_F_I32 : VOPCX_32 <0x00000090, "V_CMPX_F_I32">; -defm V_CMPX_LT_I32 : VOPCX_32 <0x00000091, "V_CMPX_LT_I32">; -defm V_CMPX_EQ_I32 : VOPCX_32 <0x00000092, "V_CMPX_EQ_I32">; -defm V_CMPX_LE_I32 : VOPCX_32 <0x00000093, "V_CMPX_LE_I32">; -defm V_CMPX_GT_I32 : VOPCX_32 <0x00000094, "V_CMPX_GT_I32">; -defm V_CMPX_NE_I32 : VOPCX_32 <0x00000095, "V_CMPX_NE_I32">; -defm V_CMPX_GE_I32 : VOPCX_32 <0x00000096, "V_CMPX_GE_I32">; -defm V_CMPX_T_I32 : VOPCX_32 <0x00000097, "V_CMPX_T_I32">; +defm V_CMPX_F_I32 : VOPCX_I32 <0x00000090, "V_CMPX_F_I32">; +defm V_CMPX_LT_I32 : VOPCX_I32 <0x00000091, "V_CMPX_LT_I32">; +defm V_CMPX_EQ_I32 : VOPCX_I32 <0x00000092, "V_CMPX_EQ_I32">; +defm V_CMPX_LE_I32 : VOPCX_I32 <0x00000093, "V_CMPX_LE_I32">; +defm V_CMPX_GT_I32 : VOPCX_I32 <0x00000094, "V_CMPX_GT_I32">; +defm V_CMPX_NE_I32 : VOPCX_I32 <0x00000095, "V_CMPX_NE_I32">; +defm V_CMPX_GE_I32 : VOPCX_I32 <0x00000096, "V_CMPX_GE_I32">; +defm V_CMPX_T_I32 : VOPCX_I32 <0x00000097, "V_CMPX_T_I32">; } // End hasSideEffects = 1 -defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">; -defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>; -defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>; -defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>; -defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>; -defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>; -defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>; -defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">; +defm V_CMP_F_I64 : VOPC_I64 <0x000000a0, "V_CMP_F_I64">; +defm V_CMP_LT_I64 : VOPC_I64 <0x000000a1, "V_CMP_LT_I64", COND_SLT>; +defm V_CMP_EQ_I64 : VOPC_I64 <0x000000a2, "V_CMP_EQ_I64", COND_EQ>; +defm V_CMP_LE_I64 : VOPC_I64 <0x000000a3, "V_CMP_LE_I64", COND_SLE>; +defm V_CMP_GT_I64 : VOPC_I64 <0x000000a4, "V_CMP_GT_I64", COND_SGT>; +defm V_CMP_NE_I64 : VOPC_I64 <0x000000a5, "V_CMP_NE_I64", COND_NE>; +defm V_CMP_GE_I64 : VOPC_I64 <0x000000a6, "V_CMP_GE_I64", COND_SGE>; +defm V_CMP_T_I64 : VOPC_I64 <0x000000a7, "V_CMP_T_I64">; let hasSideEffects = 1 in { -defm V_CMPX_F_I64 : VOPCX_64 <0x000000b0, "V_CMPX_F_I64">; -defm V_CMPX_LT_I64 : VOPCX_64 <0x000000b1, "V_CMPX_LT_I64">; -defm V_CMPX_EQ_I64 : VOPCX_64 <0x000000b2, "V_CMPX_EQ_I64">; -defm V_CMPX_LE_I64 : VOPCX_64 <0x000000b3, "V_CMPX_LE_I64">; -defm V_CMPX_GT_I64 : VOPCX_64 <0x000000b4, "V_CMPX_GT_I64">; -defm V_CMPX_NE_I64 : VOPCX_64 <0x000000b5, "V_CMPX_NE_I64">; -defm V_CMPX_GE_I64 : VOPCX_64 <0x000000b6, "V_CMPX_GE_I64">; -defm V_CMPX_T_I64 : VOPCX_64 <0x000000b7, "V_CMPX_T_I64">; +defm V_CMPX_F_I64 : VOPCX_I64 <0x000000b0, "V_CMPX_F_I64">; +defm V_CMPX_LT_I64 : VOPCX_I64 <0x000000b1, "V_CMPX_LT_I64">; +defm V_CMPX_EQ_I64 : VOPCX_I64 <0x000000b2, "V_CMPX_EQ_I64">; +defm V_CMPX_LE_I64 : VOPCX_I64 <0x000000b3, "V_CMPX_LE_I64">; +defm V_CMPX_GT_I64 : VOPCX_I64 <0x000000b4, "V_CMPX_GT_I64">; +defm V_CMPX_NE_I64 : VOPCX_I64 <0x000000b5, "V_CMPX_NE_I64">; +defm V_CMPX_GE_I64 : VOPCX_I64 <0x000000b6, "V_CMPX_GE_I64">; +defm V_CMPX_T_I64 : VOPCX_I64 <0x000000b7, "V_CMPX_T_I64">; } // End hasSideEffects = 1 -defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">; -defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>; -defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>; -defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>; -defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>; -defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>; -defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>; -defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">; +defm V_CMP_F_U32 : VOPC_I32 <0x000000c0, "V_CMP_F_U32">; +defm V_CMP_LT_U32 : VOPC_I32 <0x000000c1, "V_CMP_LT_U32", COND_ULT>; +defm V_CMP_EQ_U32 : VOPC_I32 <0x000000c2, "V_CMP_EQ_U32", COND_EQ>; +defm V_CMP_LE_U32 : VOPC_I32 <0x000000c3, "V_CMP_LE_U32", COND_ULE>; +defm V_CMP_GT_U32 : VOPC_I32 <0x000000c4, "V_CMP_GT_U32", COND_UGT>; +defm V_CMP_NE_U32 : VOPC_I32 <0x000000c5, "V_CMP_NE_U32", COND_NE>; +defm V_CMP_GE_U32 : VOPC_I32 <0x000000c6, "V_CMP_GE_U32", COND_UGE>; +defm V_CMP_T_U32 : VOPC_I32 <0x000000c7, "V_CMP_T_U32">; let hasSideEffects = 1 in { -defm V_CMPX_F_U32 : VOPCX_32 <0x000000d0, "V_CMPX_F_U32">; -defm V_CMPX_LT_U32 : VOPCX_32 <0x000000d1, "V_CMPX_LT_U32">; -defm V_CMPX_EQ_U32 : VOPCX_32 <0x000000d2, "V_CMPX_EQ_U32">; -defm V_CMPX_LE_U32 : VOPCX_32 <0x000000d3, "V_CMPX_LE_U32">; -defm V_CMPX_GT_U32 : VOPCX_32 <0x000000d4, "V_CMPX_GT_U32">; -defm V_CMPX_NE_U32 : VOPCX_32 <0x000000d5, "V_CMPX_NE_U32">; -defm V_CMPX_GE_U32 : VOPCX_32 <0x000000d6, "V_CMPX_GE_U32">; -defm V_CMPX_T_U32 : VOPCX_32 <0x000000d7, "V_CMPX_T_U32">; +defm V_CMPX_F_U32 : VOPCX_I32 <0x000000d0, "V_CMPX_F_U32">; +defm V_CMPX_LT_U32 : VOPCX_I32 <0x000000d1, "V_CMPX_LT_U32">; +defm V_CMPX_EQ_U32 : VOPCX_I32 <0x000000d2, "V_CMPX_EQ_U32">; +defm V_CMPX_LE_U32 : VOPCX_I32 <0x000000d3, "V_CMPX_LE_U32">; +defm V_CMPX_GT_U32 : VOPCX_I32 <0x000000d4, "V_CMPX_GT_U32">; +defm V_CMPX_NE_U32 : VOPCX_I32 <0x000000d5, "V_CMPX_NE_U32">; +defm V_CMPX_GE_U32 : VOPCX_I32 <0x000000d6, "V_CMPX_GE_U32">; +defm V_CMPX_T_U32 : VOPCX_I32 <0x000000d7, "V_CMPX_T_U32">; } // End hasSideEffects = 1 -defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">; -defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>; -defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>; -defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>; -defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>; -defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>; -defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>; -defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">; +defm V_CMP_F_U64 : VOPC_I64 <0x000000e0, "V_CMP_F_U64">; +defm V_CMP_LT_U64 : VOPC_I64 <0x000000e1, "V_CMP_LT_U64", COND_ULT>; +defm V_CMP_EQ_U64 : VOPC_I64 <0x000000e2, "V_CMP_EQ_U64", COND_EQ>; +defm V_CMP_LE_U64 : VOPC_I64 <0x000000e3, "V_CMP_LE_U64", COND_ULE>; +defm V_CMP_GT_U64 : VOPC_I64 <0x000000e4, "V_CMP_GT_U64", COND_UGT>; +defm V_CMP_NE_U64 : VOPC_I64 <0x000000e5, "V_CMP_NE_U64", COND_NE>; +defm V_CMP_GE_U64 : VOPC_I64 <0x000000e6, "V_CMP_GE_U64", COND_UGE>; +defm V_CMP_T_U64 : VOPC_I64 <0x000000e7, "V_CMP_T_U64">; let hasSideEffects = 1 in { -defm V_CMPX_F_U64 : VOPCX_64 <0x000000f0, "V_CMPX_F_U64">; -defm V_CMPX_LT_U64 : VOPCX_64 <0x000000f1, "V_CMPX_LT_U64">; -defm V_CMPX_EQ_U64 : VOPCX_64 <0x000000f2, "V_CMPX_EQ_U64">; -defm V_CMPX_LE_U64 : VOPCX_64 <0x000000f3, "V_CMPX_LE_U64">; -defm V_CMPX_GT_U64 : VOPCX_64 <0x000000f4, "V_CMPX_GT_U64">; -defm V_CMPX_NE_U64 : VOPCX_64 <0x000000f5, "V_CMPX_NE_U64">; -defm V_CMPX_GE_U64 : VOPCX_64 <0x000000f6, "V_CMPX_GE_U64">; -defm V_CMPX_T_U64 : VOPCX_64 <0x000000f7, "V_CMPX_T_U64">; +defm V_CMPX_F_U64 : VOPCX_I64 <0x000000f0, "V_CMPX_F_U64">; +defm V_CMPX_LT_U64 : VOPCX_I64 <0x000000f1, "V_CMPX_LT_U64">; +defm V_CMPX_EQ_U64 : VOPCX_I64 <0x000000f2, "V_CMPX_EQ_U64">; +defm V_CMPX_LE_U64 : VOPCX_I64 <0x000000f3, "V_CMPX_LE_U64">; +defm V_CMPX_GT_U64 : VOPCX_I64 <0x000000f4, "V_CMPX_GT_U64">; +defm V_CMPX_NE_U64 : VOPCX_I64 <0x000000f5, "V_CMPX_NE_U64">; +defm V_CMPX_GE_U64 : VOPCX_I64 <0x000000f6, "V_CMPX_GE_U64">; +defm V_CMPX_T_U64 : VOPCX_I64 <0x000000f7, "V_CMPX_T_U64">; } // End hasSideEffects = 1 -defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">; +defm V_CMP_CLASS_F32 : VOPC_F32 <0x00000088, "V_CMP_CLASS_F32">; let hasSideEffects = 1 in { -defm V_CMPX_CLASS_F32 : VOPCX_32 <0x00000098, "V_CMPX_CLASS_F32">; +defm V_CMPX_CLASS_F32 : VOPCX_F32 <0x00000098, "V_CMPX_CLASS_F32">; } // End hasSideEffects = 1 -defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">; +defm V_CMP_CLASS_F64 : VOPC_F64 <0x000000a8, "V_CMP_CLASS_F64">; let hasSideEffects = 1 in { -defm V_CMPX_CLASS_F64 : VOPCX_64 <0x000000b8, "V_CMPX_CLASS_F64">; +defm V_CMPX_CLASS_F64 : VOPCX_F64 <0x000000b8, "V_CMPX_CLASS_F64">; } // End hasSideEffects = 1 } // End isCompare = 1 @@ -1045,7 +1045,7 @@ defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "IMAGE_SAMPLE_C_CD_CL_O" //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; let isMoveImm = 1 in { -defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; +defm V_MOV_B32 : VOP1Inst <0x00000001, "V_MOV_B32", VOP_I32_I32>; } // End isMoveImm = 1 let Uses = [EXEC] in { @@ -1060,134 +1060,134 @@ def V_READFIRSTLANE_B32 : VOP1 < } -defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64", - [(set i32:$dst, (fp_to_sint f64:$src0))] +defm V_CVT_I32_F64 : VOP1Inst <0x00000003, "V_CVT_I32_F64", + VOP_I32_F64, fp_to_sint >; -defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32", - [(set f64:$dst, (sint_to_fp i32:$src0))] +defm V_CVT_F64_I32 : VOP1Inst <0x00000004, "V_CVT_F64_I32", + VOP_F64_I32, sint_to_fp >; -defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", - [(set f32:$dst, (sint_to_fp i32:$src0))] +defm V_CVT_F32_I32 : VOP1Inst <0x00000005, "V_CVT_F32_I32", + VOP_F32_I32, sint_to_fp >; -defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", - [(set f32:$dst, (uint_to_fp i32:$src0))] +defm V_CVT_F32_U32 : VOP1Inst <0x00000006, "V_CVT_F32_U32", + VOP_F32_I32, uint_to_fp >; -defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", - [(set i32:$dst, (fp_to_uint f32:$src0))] +defm V_CVT_U32_F32 : VOP1Inst <0x00000007, "V_CVT_U32_F32", + VOP_I32_F32, fp_to_uint >; -defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", - [(set i32:$dst, (fp_to_sint f32:$src0))] +defm V_CVT_I32_F32 : VOP1Inst <0x00000008, "V_CVT_I32_F32", + VOP_I32_F32, fp_to_sint >; -defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; -defm V_CVT_F16_F32 : VOP1_32 <0x0000000a, "V_CVT_F16_F32", - [(set i32:$dst, (fp_to_f16 f32:$src0))] +defm V_MOV_FED_B32 : VOP1Inst <0x00000009, "V_MOV_FED_B32", VOP_I32_I32>; +defm V_CVT_F16_F32 : VOP1Inst <0x0000000a, "V_CVT_F16_F32", + VOP_I32_F32, fp_to_f16 >; -defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", - [(set f32:$dst, (f16_to_fp i32:$src0))] +defm V_CVT_F32_F16 : VOP1Inst <0x0000000b, "V_CVT_F32_F16", + VOP_F32_I32, f16_to_fp >; //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; -defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64", - [(set f32:$dst, (fround f64:$src0))] +defm V_CVT_F32_F64 : VOP1Inst <0x0000000f, "V_CVT_F32_F64", + VOP_F32_F64, fround >; -defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32", - [(set f64:$dst, (fextend f32:$src0))] +defm V_CVT_F64_F32 : VOP1Inst <0x00000010, "V_CVT_F64_F32", + VOP_F64_F32, fextend >; -defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", - [(set f32:$dst, (AMDGPUcvt_f32_ubyte0 i32:$src0))] +defm V_CVT_F32_UBYTE0 : VOP1Inst <0x00000011, "V_CVT_F32_UBYTE0", + VOP_F32_I32, AMDGPUcvt_f32_ubyte0 >; -defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", - [(set f32:$dst, (AMDGPUcvt_f32_ubyte1 i32:$src0))] +defm V_CVT_F32_UBYTE1 : VOP1Inst <0x00000012, "V_CVT_F32_UBYTE1", + VOP_F32_I32, AMDGPUcvt_f32_ubyte1 >; -defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", - [(set f32:$dst, (AMDGPUcvt_f32_ubyte2 i32:$src0))] +defm V_CVT_F32_UBYTE2 : VOP1Inst <0x00000013, "V_CVT_F32_UBYTE2", + VOP_F32_I32, AMDGPUcvt_f32_ubyte2 >; -defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", - [(set f32:$dst, (AMDGPUcvt_f32_ubyte3 i32:$src0))] +defm V_CVT_F32_UBYTE3 : VOP1Inst <0x00000014, "V_CVT_F32_UBYTE3", + VOP_F32_I32, AMDGPUcvt_f32_ubyte3 >; -defm V_CVT_U32_F64 : VOP1_32_64 <0x00000015, "V_CVT_U32_F64", - [(set i32:$dst, (fp_to_uint f64:$src0))] +defm V_CVT_U32_F64 : VOP1Inst <0x00000015, "V_CVT_U32_F64", + VOP_I32_F64, fp_to_uint >; -defm V_CVT_F64_U32 : VOP1_64_32 <0x00000016, "V_CVT_F64_U32", - [(set f64:$dst, (uint_to_fp i32:$src0))] +defm V_CVT_F64_U32 : VOP1Inst <0x00000016, "V_CVT_F64_U32", + VOP_F64_I32, uint_to_fp >; -defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", - [(set f32:$dst, (AMDGPUfract f32:$src0))] +defm V_FRACT_F32 : VOP1Inst <0x00000020, "V_FRACT_F32", + VOP_F32_F32, AMDGPUfract >; -defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", - [(set f32:$dst, (ftrunc f32:$src0))] +defm V_TRUNC_F32 : VOP1Inst <0x00000021, "V_TRUNC_F32", + VOP_F32_F32, ftrunc >; -defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", - [(set f32:$dst, (fceil f32:$src0))] +defm V_CEIL_F32 : VOP1Inst <0x00000022, "V_CEIL_F32", + VOP_F32_F32, fceil >; -defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", - [(set f32:$dst, (frint f32:$src0))] +defm V_RNDNE_F32 : VOP1Inst <0x00000023, "V_RNDNE_F32", + VOP_F32_F32, frint >; -defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", - [(set f32:$dst, (ffloor f32:$src0))] +defm V_FLOOR_F32 : VOP1Inst <0x00000024, "V_FLOOR_F32", + VOP_F32_F32, ffloor >; -defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", - [(set f32:$dst, (fexp2 f32:$src0))] +defm V_EXP_F32 : VOP1Inst <0x00000025, "V_EXP_F32", + VOP_F32_F32, fexp2 >; -defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; -defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", - [(set f32:$dst, (flog2 f32:$src0))] +defm V_LOG_CLAMP_F32 : VOP1Inst <0x00000026, "V_LOG_CLAMP_F32", VOP_F32_F32>; +defm V_LOG_F32 : VOP1Inst <0x00000027, "V_LOG_F32", + VOP_F32_F32, flog2 >; -defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; -defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; -defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", - [(set f32:$dst, (AMDGPUrcp f32:$src0))] +defm V_RCP_CLAMP_F32 : VOP1Inst <0x00000028, "V_RCP_CLAMP_F32", VOP_F32_F32>; +defm V_RCP_LEGACY_F32 : VOP1Inst <0x00000029, "V_RCP_LEGACY_F32", VOP_F32_F32>; +defm V_RCP_F32 : VOP1Inst <0x0000002a, "V_RCP_F32", + VOP_F32_F32, AMDGPUrcp >; -defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; -defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", - [(set f32:$dst, (AMDGPUrsq_clamped f32:$src0))] +defm V_RCP_IFLAG_F32 : VOP1Inst <0x0000002b, "V_RCP_IFLAG_F32", VOP_F32_F32>; +defm V_RSQ_CLAMP_F32 : VOP1Inst <0x0000002c, "V_RSQ_CLAMP_F32", + VOP_F32_F32, AMDGPUrsq_clamped >; -defm V_RSQ_LEGACY_F32 : VOP1_32 < +defm V_RSQ_LEGACY_F32 : VOP1Inst < 0x0000002d, "V_RSQ_LEGACY_F32", - [(set f32:$dst, (AMDGPUrsq_legacy f32:$src0))] + VOP_F32_F32, AMDGPUrsq_legacy >; -defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", - [(set f32:$dst, (AMDGPUrsq f32:$src0))] +defm V_RSQ_F32 : VOP1Inst <0x0000002e, "V_RSQ_F32", + VOP_F32_F32, AMDGPUrsq >; -defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", - [(set f64:$dst, (AMDGPUrcp f64:$src0))] +defm V_RCP_F64 : VOP1Inst <0x0000002f, "V_RCP_F64", + VOP_F64_F64, AMDGPUrcp >; -defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; -defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", - [(set f64:$dst, (AMDGPUrsq f64:$src0))] +defm V_RCP_CLAMP_F64 : VOP1Inst <0x00000030, "V_RCP_CLAMP_F64", VOP_F64_F64>; +defm V_RSQ_F64 : VOP1Inst <0x00000031, "V_RSQ_F64", + VOP_F64_F64, AMDGPUrsq >; -defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", - [(set f64:$dst, (AMDGPUrsq_clamped f64:$src0))] +defm V_RSQ_CLAMP_F64 : VOP1Inst <0x00000032, "V_RSQ_CLAMP_F64", + VOP_F64_F64, AMDGPUrsq_clamped >; -defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", - [(set f32:$dst, (fsqrt f32:$src0))] +defm V_SQRT_F32 : VOP1Inst <0x00000033, "V_SQRT_F32", + VOP_F32_F32, fsqrt >; -defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", - [(set f64:$dst, (fsqrt f64:$src0))] +defm V_SQRT_F64 : VOP1Inst <0x00000034, "V_SQRT_F64", + VOP_F64_F64, fsqrt >; -defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", - [(set f32:$dst, (AMDGPUsin f32:$src0))] +defm V_SIN_F32 : VOP1Inst <0x00000035, "V_SIN_F32", + VOP_F32_F32, AMDGPUsin >; -defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", - [(set f32:$dst, (AMDGPUcos f32:$src0))] +defm V_COS_F32 : VOP1Inst <0x00000036, "V_COS_F32", + VOP_F32_F32, AMDGPUcos >; -defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; -defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; -defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; -defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; -defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; -//defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; -defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; -defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; -//defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; -defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; +defm V_NOT_B32 : VOP1Inst <0x00000037, "V_NOT_B32", VOP_I32_I32>; +defm V_BFREV_B32 : VOP1Inst <0x00000038, "V_BFREV_B32", VOP_I32_I32>; +defm V_FFBH_U32 : VOP1Inst <0x00000039, "V_FFBH_U32", VOP_I32_I32>; +defm V_FFBL_B32 : VOP1Inst <0x0000003a, "V_FFBL_B32", VOP_I32_I32>; +defm V_FFBH_I32 : VOP1Inst <0x0000003b, "V_FFBH_I32", VOP_I32_I32>; +//defm V_FREXP_EXP_I32_F64 : VOPInst <0x0000003c, "V_FREXP_EXP_I32_F64", VOP_I32_F32>; +defm V_FREXP_MANT_F64 : VOP1Inst <0x0000003d, "V_FREXP_MANT_F64", VOP_F64_F64>; +defm V_FRACT_F64 : VOP1Inst <0x0000003e, "V_FRACT_F64", VOP_F64_F64>; +//defm V_FREXP_EXP_I32_F32 : VOPInst <0x0000003f, "V_FREXP_EXP_I32_F32", VOP_I32_F32>; +defm V_FREXP_MANT_F32 : VOP1Inst <0x00000040, "V_FREXP_MANT_F32", VOP_F32_F32>; //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; -defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; -defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; -defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; +defm V_MOVRELD_B32 : VOP1Inst <0x00000042, "V_MOVRELD_B32", VOP_I32_I32>; +defm V_MOVRELS_B32 : VOP1Inst <0x00000043, "V_MOVRELS_B32", VOP_I32_I32>; +defm V_MOVRELSD_B32 : VOP1Inst <0x00000044, "V_MOVRELSD_B32", VOP_I32_I32>; //===----------------------------------------------------------------------===// @@ -1264,125 +1264,138 @@ def V_WRITELANE_B32 : VOP2 < >; let isCommutable = 1 in { -defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", - [(set f32:$dst, (fadd f32:$src0, f32:$src1))] +defm V_ADD_F32 : VOP2Inst <0x00000003, "V_ADD_F32", + VOP_F32_F32_F32, fadd >; -defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", - [(set f32:$dst, (fsub f32:$src0, f32:$src1))] +defm V_SUB_F32 : VOP2Inst <0x00000004, "V_SUB_F32", VOP_F32_F32_F32, fsub>; +defm V_SUBREV_F32 : VOP2Inst <0x00000005, "V_SUBREV_F32", + VOP_F32_F32_F32, null_frag, "V_SUB_F32" >; -defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">; } // End isCommutable = 1 -defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; +defm V_MAC_LEGACY_F32 : VOP2Inst <0x00000006, "V_MAC_LEGACY_F32", + VOP_F32_F32_F32 +>; let isCommutable = 1 in { -defm V_MUL_LEGACY_F32 : VOP2_32 < +defm V_MUL_LEGACY_F32 : VOP2Inst < 0x00000007, "V_MUL_LEGACY_F32", - [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))] + VOP_F32_F32_F32, int_AMDGPU_mul >; -defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", - [(set f32:$dst, (fmul f32:$src0, f32:$src1))] +defm V_MUL_F32 : VOP2Inst <0x00000008, "V_MUL_F32", + VOP_F32_F32_F32, fmul >; -defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", - [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))] +defm V_MUL_I32_I24 : VOP2Inst <0x00000009, "V_MUL_I32_I24", + VOP_I32_I32_I32, AMDGPUmul_i24 >; //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; -defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", - [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))] +defm V_MUL_U32_U24 : VOP2Inst <0x0000000b, "V_MUL_U32_U24", + VOP_I32_I32_I32, AMDGPUmul_u24 >; //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; -defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", - [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))] +defm V_MIN_LEGACY_F32 : VOP2Inst <0x0000000d, "V_MIN_LEGACY_F32", + VOP_F32_F32_F32, AMDGPUfmin >; -defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", - [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))] +defm V_MAX_LEGACY_F32 : VOP2Inst <0x0000000e, "V_MAX_LEGACY_F32", + VOP_F32_F32_F32, AMDGPUfmax >; -defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; -defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; -defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", - [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]>; -defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", - [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]>; -defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", - [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]>; -defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", - [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]>; +defm V_MIN_F32 : VOP2Inst <0x0000000f, "V_MIN_F32", VOP_F32_F32_F32>; +defm V_MAX_F32 : VOP2Inst <0x00000010, "V_MAX_F32", VOP_F32_F32_F32>; +defm V_MIN_I32 : VOP2Inst <0x00000011, "V_MIN_I32", VOP_I32_I32_I32, AMDGPUsmin>; +defm V_MAX_I32 : VOP2Inst <0x00000012, "V_MAX_I32", VOP_I32_I32_I32, AMDGPUsmax>; +defm V_MIN_U32 : VOP2Inst <0x00000013, "V_MIN_U32", VOP_I32_I32_I32, AMDGPUumin>; +defm V_MAX_U32 : VOP2Inst <0x00000014, "V_MAX_U32", VOP_I32_I32_I32, AMDGPUumax>; -defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", - [(set i32:$dst, (srl i32:$src0, i32:$src1))] ->; +defm V_LSHR_B32 : VOP2Inst <0x00000015, "V_LSHR_B32", VOP_I32_I32_I32, srl>; -defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">; +defm V_LSHRREV_B32 : VOP2Inst < + 0x00000016, "V_LSHRREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHR_B32" +>; -defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", - [(set i32:$dst, (sra i32:$src0, i32:$src1))] +defm V_ASHR_I32 : VOP2Inst <0x00000017, "V_ASHR_I32", + VOP_I32_I32_I32, sra +>; +defm V_ASHRREV_I32 : VOP2Inst < + 0x00000018, "V_ASHRREV_I32", VOP_I32_I32_I32, null_frag, "V_ASHR_I32" >; -defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">; let hasPostISelHook = 1 in { -defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", - [(set i32:$dst, (shl i32:$src0, i32:$src1))] ->; +defm V_LSHL_B32 : VOP2Inst <0x00000019, "V_LSHL_B32", VOP_I32_I32_I32, shl>; } -defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">; +defm V_LSHLREV_B32 : VOP2Inst < + 0x0000001a, "V_LSHLREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHL_B32" +>; -defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", - [(set i32:$dst, (and i32:$src0, i32:$src1))]>; -defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", - [(set i32:$dst, (or i32:$src0, i32:$src1))] +defm V_AND_B32 : VOP2Inst <0x0000001b, "V_AND_B32", + VOP_I32_I32_I32, and>; +defm V_OR_B32 : VOP2Inst <0x0000001c, "V_OR_B32", + VOP_I32_I32_I32, or >; -defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", - [(set i32:$dst, (xor i32:$src0, i32:$src1))] +defm V_XOR_B32 : VOP2Inst <0x0000001d, "V_XOR_B32", + VOP_I32_I32_I32, xor >; } // End isCommutable = 1 -defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", - [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>; -defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; -defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; -defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; -defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; -defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; -defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; +defm V_BFM_B32 : VOP2Inst <0x0000001e, "V_BFM_B32", + VOP_I32_I32_I32, AMDGPUbfm>; +defm V_MAC_F32 : VOP2Inst <0x0000001f, "V_MAC_F32", VOP_F32_F32_F32>; +defm V_MADMK_F32 : VOP2Inst <0x00000020, "V_MADMK_F32", VOP_F32_F32_F32>; +defm V_MADAK_F32 : VOP2Inst <0x00000021, "V_MADAK_F32", VOP_F32_F32_F32>; +defm V_BCNT_U32_B32 : VOP2Inst <0x00000022, "V_BCNT_U32_B32", VOP_I32_I32_I32>; +defm V_MBCNT_LO_U32_B32 : VOP2Inst <0x00000023, "V_MBCNT_LO_U32_B32", + VOP_I32_I32_I32 +>; +defm V_MBCNT_HI_U32_B32 : VOP2Inst <0x00000024, "V_MBCNT_HI_U32_B32", + VOP_I32_I32_I32 +>; let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC // No patterns so that the scalar instructions are always selected. // The scalar versions will be replaced with vector when needed later. -defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", - [(set i32:$dst, (add i32:$src0, i32:$src1))], VSrc_32>; -defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", - [(set i32:$dst, (sub i32:$src0, i32:$src1))], VSrc_32>; -defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32, - "V_SUB_I32">; +defm V_ADD_I32 : VOP2bInst <0x00000025, "V_ADD_I32", + VOP_I32_I32_I32, add +>; +defm V_SUB_I32 : VOP2bInst <0x00000026, "V_SUB_I32", + VOP_I32_I32_I32, sub +>; +defm V_SUBREV_I32 : VOP2bInst <0x00000027, "V_SUBREV_I32", + VOP_I32_I32_I32, null_frag, "V_SUB_I32" +>; let Uses = [VCC] in { // Carry-in comes from VCC -defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", - [(set i32:$dst, (adde i32:$src0, i32:$src1))], VReg_32>; -defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", - [(set i32:$dst, (sube i32:$src0, i32:$src1))], VReg_32>; -defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32, - "V_SUBB_U32">; +defm V_ADDC_U32 : VOP2bInst <0x00000028, "V_ADDC_U32", + VOP_I32_I32_I32_VCC, adde +>; +defm V_SUBB_U32 : VOP2bInst <0x00000029, "V_SUBB_U32", + VOP_I32_I32_I32_VCC, sube +>; +defm V_SUBBREV_U32 : VOP2bInst <0x0000002a, "V_SUBBREV_U32", + VOP_I32_I32_I32_VCC, null_frag, "V_SUBB_U32" +>; + } // End Uses = [VCC] } // End isCommutable = 1, Defs = [VCC] -defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; +defm V_LDEXP_F32 : VOP2Inst <0x0000002b, "V_LDEXP_F32", + VOP_F32_F32_F32 +>; ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; -defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", - [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))] +defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <0x0000002f, "V_CVT_PKRTZ_F16_F32", + VOP_I32_F32_F32, int_SI_packf16 >; ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; @@ -1391,40 +1404,59 @@ defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", // VOP3 Instructions //===----------------------------------------------------------------------===// -defm V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; -defm V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", - [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))] +defm V_MAD_LEGACY_F32 : VOP3Inst <0x00000140, "V_MAD_LEGACY_F32", + VOP_F32_F32_F32_F32 +>; +defm V_MAD_F32 : VOP3Inst <0x00000141, "V_MAD_F32", + VOP_F32_F32_F32_F32, fmad >; -defm V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", - [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))] +defm V_MAD_I32_I24 : VOP3Inst <0x00000142, "V_MAD_I32_I24", + VOP_I32_I32_I32_I32, AMDGPUmad_i24 >; -defm V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", - [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))] +defm V_MAD_U32_U24 : VOP3Inst <0x00000143, "V_MAD_U32_U24", + VOP_I32_I32_I32_I32, AMDGPUmad_u24 >; -defm V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; -defm V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; -defm V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; -defm V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; +defm V_CUBEID_F32 : VOP3Inst <0x00000144, "V_CUBEID_F32", + VOP_F32_F32_F32_F32 +>; +defm V_CUBESC_F32 : VOP3Inst <0x00000145, "V_CUBESC_F32", + VOP_F32_F32_F32_F32 +>; +defm V_CUBETC_F32 : VOP3Inst <0x00000146, "V_CUBETC_F32", + VOP_F32_F32_F32_F32 +>; +defm V_CUBEMA_F32 : VOP3Inst <0x00000147, "V_CUBEMA_F32", + VOP_F32_F32_F32_F32 +>; -defm V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", - [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))]>; -defm V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", - [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>; +let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in { +defm V_BFE_U32 : VOP3Inst <0x00000148, "V_BFE_U32", + VOP_I32_I32_I32_I32, AMDGPUbfe_u32 +>; +defm V_BFE_I32 : VOP3Inst <0x00000149, "V_BFE_I32", + VOP_I32_I32_I32_I32, AMDGPUbfe_i32 +>; +} -defm V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", - [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))]>; -defm V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", - [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))] +defm V_BFI_B32 : VOP3Inst <0x0000014a, "V_BFI_B32", + VOP_I32_I32_I32_I32, AMDGPUbfi >; -def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", - [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] +defm V_FMA_F32 : VOP3Inst <0x0000014b, "V_FMA_F32", + VOP_F32_F32_F32_F32, fma +>; +defm V_FMA_F64 : VOP3Inst <0x0000014c, "V_FMA_F64", + VOP_F64_F64_F64_F64, fma >; //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; -defm V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; - -defm V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; -defm V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; +defm V_ALIGNBIT_B32 : VOP3Inst <0x0000014e, "V_ALIGNBIT_B32", + VOP_I32_I32_I32_I32 +>; +defm V_ALIGNBYTE_B32 : VOP3Inst <0x0000014f, "V_ALIGNBYTE_B32", + VOP_I32_I32_I32_I32 +>; +defm V_MULLIT_F32 : VOP3Inst <0x00000150, "V_MULLIT_F32", + VOP_F32_F32_F32_F32>; ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; @@ -1437,61 +1469,81 @@ defm V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; -defm V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; +defm V_SAD_U32 : VOP3Inst <0x0000015d, "V_SAD_U32", + VOP_I32_I32_I32_I32 +>; ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; -defm V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", - [(set f32:$dst, (AMDGPUdiv_fixup f32:$src0, f32:$src1, f32:$src2))] +defm V_DIV_FIXUP_F32 : VOP3Inst < + 0x0000015f, "V_DIV_FIXUP_F32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup >; -def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", - [(set f64:$dst, (AMDGPUdiv_fixup f64:$src0, f64:$src1, f64:$src2))] +defm V_DIV_FIXUP_F64 : VOP3Inst < + 0x00000160, "V_DIV_FIXUP_F64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup >; -def V_LSHL_B64 : VOP3_64_32 <0x00000161, "V_LSHL_B64", - [(set i64:$dst, (shl i64:$src0, i32:$src1))] +defm V_LSHL_B64 : VOP3Inst <0x00000161, "V_LSHL_B64", + VOP_I64_I64_I32, shl >; -def V_LSHR_B64 : VOP3_64_32 <0x00000162, "V_LSHR_B64", - [(set i64:$dst, (srl i64:$src0, i32:$src1))] +defm V_LSHR_B64 : VOP3Inst <0x00000162, "V_LSHR_B64", + VOP_I64_I64_I32, srl >; -def V_ASHR_I64 : VOP3_64_32 <0x00000163, "V_ASHR_I64", - [(set i64:$dst, (sra i64:$src0, i32:$src1))] +defm V_ASHR_I64 : VOP3Inst <0x00000163, "V_ASHR_I64", + VOP_I64_I64_I32, sra >; let isCommutable = 1 in { -def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; -def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; -def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; -def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; +defm V_ADD_F64 : VOP3Inst <0x00000164, "V_ADD_F64", + VOP_F64_F64_F64, fadd +>; +defm V_MUL_F64 : VOP3Inst <0x00000165, "V_MUL_F64", + VOP_F64_F64_F64, fmul +>; +defm V_MIN_F64 : VOP3Inst <0x00000166, "V_MIN_F64", + VOP_F64_F64_F64 +>; +defm V_MAX_F64 : VOP3Inst <0x00000167, "V_MAX_F64", + VOP_F64_F64_F64 +>; } // isCommutable = 1 -def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; +defm V_LDEXP_F64 : VOP3Inst <0x00000168, "V_LDEXP_F64", + VOP_F32_F32_I32 +>; let isCommutable = 1 in { -defm V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; -defm V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; -defm V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; -defm V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; +defm V_MUL_LO_U32 : VOP3Inst <0x00000169, "V_MUL_LO_U32", + VOP_I32_I32_I32 +>; +defm V_MUL_HI_U32 : VOP3Inst <0x0000016a, "V_MUL_HI_U32", + VOP_I32_I32_I32 +>; +defm V_MUL_LO_I32 : VOP3Inst <0x0000016b, "V_MUL_LO_I32", + VOP_I32_I32_I32 +>; +defm V_MUL_HI_I32 : VOP3Inst <0x0000016c, "V_MUL_HI_I32", + VOP_I32_I32_I32 +>; } // isCommutable = 1 -def V_DIV_SCALE_F32 : VOP3b_32 <0x0000016d, "V_DIV_SCALE_F32", []>; +defm V_DIV_SCALE_F32 : VOP3b_32 <0x0000016d, "V_DIV_SCALE_F32", []>; // Double precision division pre-scale. -def V_DIV_SCALE_F64 : VOP3b_64 <0x0000016e, "V_DIV_SCALE_F64", []>; +defm V_DIV_SCALE_F64 : VOP3b_64 <0x0000016e, "V_DIV_SCALE_F64", []>; -defm V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", - [(set f32:$dst, (AMDGPUdiv_fmas f32:$src0, f32:$src1, f32:$src2))] +defm V_DIV_FMAS_F32 : VOP3Inst <0x0000016f, "V_DIV_FMAS_F32", + VOP_F32_F32_F32_F32, AMDGPUdiv_fmas >; -def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", - [(set f64:$dst, (AMDGPUdiv_fmas f64:$src0, f64:$src1, f64:$src2))] +defm V_DIV_FMAS_F64 : VOP3Inst <0x00000170, "V_DIV_FMAS_F64", + VOP_F64_F64_F64_F64, AMDGPUdiv_fmas >; //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; -def V_TRIG_PREOP_F64 : VOP3_64_32 <0x00000174, "V_TRIG_PREOP_F64", - [(set f64:$dst, (AMDGPUtrig_preop f64:$src0, i32:$src1))] +defm V_TRIG_PREOP_F64 : VOP3Inst < + 0x00000174, "V_TRIG_PREOP_F64", VOP_F64_F64_I32, AMDGPUtrig_preop >; //===----------------------------------------------------------------------===// @@ -1713,7 +1765,9 @@ let Predicates = [isSI] in { def : Pat< (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2), - (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0)) + (V_CNDMASK_B32_e64 $src2, $src1, + (V_CMP_GT_F32_e64 SRCMODS.NONE, 0, SRCMODS.NONE, $src0, + DSTCLAMP.NONE, DSTOMOD.NONE)) >; def : Pat < @@ -1860,7 +1914,7 @@ def : Pat < def : Pat < (i32 (ctpop i32:$popcnt)), - (V_BCNT_U32_B32_e64 $popcnt, 0, 0, 0) + (V_BCNT_U32_B32_e64 $popcnt, 0) >; def : Pat < @@ -1868,7 +1922,7 @@ def : Pat < (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (V_BCNT_U32_B32_e32 (EXTRACT_SUBREG $src, sub1), - (V_BCNT_U32_B32_e64 (EXTRACT_SUBREG $src, sub0), 0, 0, 0)), + (V_BCNT_U32_B32_e64 (EXTRACT_SUBREG $src, sub0), 0)), sub0), (V_MOV_B32_e32 0), sub1) >; @@ -2367,28 +2421,34 @@ def : Pat < def : Pat< (fdiv f64:$src0, f64:$src1), - (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0)) + (V_MUL_F64 0 /* src0_modifiers */, $src0, + 0 /* src1_modifiers */, (V_RCP_F64_e32 $src1), + 0 /* clamp */, 0 /* omod */) >; def : Pat < (int_AMDGPU_cube v4f32:$src), (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), - (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0), - (EXTRACT_SUBREG $src, sub1), - (EXTRACT_SUBREG $src, sub2)), - sub0), - (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0), - (EXTRACT_SUBREG $src, sub1), - (EXTRACT_SUBREG $src, sub2)), - sub1), - (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0), - (EXTRACT_SUBREG $src, sub1), - (EXTRACT_SUBREG $src, sub2)), - sub2), - (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0), - (EXTRACT_SUBREG $src, sub1), - (EXTRACT_SUBREG $src, sub2)), - sub3) + (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0), + 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1), + 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2), + 0 /* clamp */, 0 /* omod */), + sub0), + (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0), + 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), + 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2), + 0 /* clamp */, 0 /* omod */), + sub1), + (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0), + 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), + 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2), + 0 /* clamp */, 0 /* omod */), + sub2), + (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0), + 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), + 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2), + 0 /* clamp */, 0 /* omod */), + sub3) >; def : Pat < @@ -2421,7 +2481,7 @@ def : Pat < def : Pat < (int_SI_tid), (V_MBCNT_HI_U32_B32_e32 0xffffffff, - (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0)) + (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0)) >; //===----------------------------------------------------------------------===// @@ -2431,29 +2491,19 @@ def : Pat < def : IMad24Pat; def : UMad24Pat; -def : Pat < - (fadd f64:$src0, f64:$src1), - (V_ADD_F64 $src0, $src1, (i64 0)) ->; - -def : Pat < - (fmul f64:$src0, f64:$src1), - (V_MUL_F64 $src0, $src1, (i64 0)) ->; - def : Pat < (mul i32:$src0, i32:$src1), - (V_MUL_LO_I32 $src0, $src1, (i32 0)) + (V_MUL_LO_I32 $src0, $src1) >; def : Pat < (mulhu i32:$src0, i32:$src1), - (V_MUL_HI_U32 $src0, $src1, (i32 0)) + (V_MUL_HI_U32 $src0, $src1) >; def : Pat < (mulhs i32:$src0, i32:$src1), - (V_MUL_HI_I32 $src0, $src1, (i32 0)) + (V_MUL_HI_I32 $src0, $src1) >; defm : BFIPatterns ; @@ -2717,26 +2767,36 @@ def : MTBUF_StoreResource ; let SubtargetPredicate = isCI in { // Sea island new arithmetic instructinos -defm V_TRUNC_F64 : VOP1_64 <0x00000017, "V_TRUNC_F64", - [(set f64:$dst, (ftrunc f64:$src0))] +defm V_TRUNC_F64 : VOP1Inst <0x00000017, "V_TRUNC_F64", + VOP_F64_F64, ftrunc >; -defm V_CEIL_F64 : VOP1_64 <0x00000018, "V_CEIL_F64", - [(set f64:$dst, (fceil f64:$src0))] +defm V_CEIL_F64 : VOP1Inst <0x00000018, "V_CEIL_F64", + VOP_F64_F64, fceil >; -defm V_FLOOR_F64 : VOP1_64 <0x0000001A, "V_FLOOR_F64", - [(set f64:$dst, (ffloor f64:$src0))] +defm V_FLOOR_F64 : VOP1Inst <0x0000001A, "V_FLOOR_F64", + VOP_F64_F64, ffloor >; -defm V_RNDNE_F64 : VOP1_64 <0x00000019, "V_RNDNE_F64", - [(set f64:$dst, (frint f64:$src0))] +defm V_RNDNE_F64 : VOP1Inst <0x00000019, "V_RNDNE_F64", + VOP_F64_F64, frint >; -defm V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>; -defm V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>; -defm V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>; -def V_MAD_U64_U32 : VOP3_64 <0x00000176, "V_MAD_U64_U32", []>; +defm V_QSAD_PK_U16_U8 : VOP3Inst <0x00000173, "V_QSAD_PK_U16_U8", + VOP_I32_I32_I32 +>; +defm V_MQSAD_U16_U8 : VOP3Inst <0x000000172, "V_MQSAD_U16_U8", + VOP_I32_I32_I32 +>; +defm V_MQSAD_U32_U8 : VOP3Inst <0x00000175, "V_MQSAD_U32_U8", + VOP_I32_I32_I32 +>; +defm V_MAD_U64_U32 : VOP3Inst <0x00000176, "V_MAD_U64_U32", + VOP_I64_I32_I32_I64 +>; // XXX - Does this set VCC? -def V_MAD_I64_I32 : VOP3_64 <0x00000177, "V_MAD_I64_I32", []>; +defm V_MAD_I64_I32 : VOP3Inst <0x00000177, "V_MAD_I64_I32", + VOP_I64_I32_I32_I64 +>; // Remaining instructions: // FLAT_* diff --git a/lib/Target/R600/SILowerI1Copies.cpp b/lib/Target/R600/SILowerI1Copies.cpp index db19235995b..4ba87a5f9a1 100644 --- a/lib/Target/R600/SILowerI1Copies.cpp +++ b/lib/Target/R600/SILowerI1Copies.cpp @@ -136,11 +136,7 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) { SrcRC == &AMDGPU::VReg_1RegClass) { BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::V_CMP_NE_I32_e64)) .addOperand(MI.getOperand(0)) - .addImm(0) .addOperand(MI.getOperand(1)) - .addImm(0) - .addImm(0) - .addImm(0) .addImm(0); MI.eraseFromParent(); } diff --git a/lib/Target/R600/SIShrinkInstructions.cpp b/lib/Target/R600/SIShrinkInstructions.cpp index 529248b1557..3fd771d57b0 100644 --- a/lib/Target/R600/SIShrinkInstructions.cpp +++ b/lib/Target/R600/SIShrinkInstructions.cpp @@ -93,7 +93,7 @@ static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII, const MachineOperand *Src1Mod = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers); - if (Src1 && (!isVGPR(Src1, TRI, MRI) || Src1Mod->getImm() != 0)) + if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0))) return false; // We don't need to check src0, all input types are legal, so just make diff --git a/test/CodeGen/R600/fabs.ll b/test/CodeGen/R600/fabs.ll index b87ce225409..fa1b60861f5 100644 --- a/test/CodeGen/R600/fabs.ll +++ b/test/CodeGen/R600/fabs.ll @@ -50,8 +50,9 @@ entry: } ; SI-CHECK-LABEL: @fabs_fold +; SI-CHECK: S_LOAD_DWORD [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb ; SI-CHECK-NOT: V_AND_B32_e32 -; SI-CHECK: V_MUL_F32_e64 v{{[0-9]+}}, s{{[0-9]+}}, |v{{[0-9]+}}| +; SI-CHECK: V_MUL_F32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}} define void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) { entry: %0 = call float @fabs(float %in0) diff --git a/test/CodeGen/R600/fneg.ll b/test/CodeGen/R600/fneg.ll index 4cddc737895..5b478177ace 100644 --- a/test/CodeGen/R600/fneg.ll +++ b/test/CodeGen/R600/fneg.ll @@ -61,8 +61,9 @@ entry: } ; SI-CHECK-LABEL: @fneg_fold +; SI-CHECK: S_LOAD_DWORD [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb ; SI-CHECK-NOT: V_XOR_B32 -; SI-CHECK: V_MUL_F32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -v{{[0-9]+}} +; SI-CHECK: V_MUL_F32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], v{{[0-9]+}} define void @fneg_fold(float addrspace(1)* %out, float %in) { entry: %0 = fsub float -0.0, %in diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll index 4f74efba4d8..5fb9ff6056d 100644 --- a/test/CodeGen/R600/fsub.ll +++ b/test/CodeGen/R600/fsub.ll @@ -20,8 +20,8 @@ declare void @llvm.AMDGPU.store.output(float, i32) ; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z ; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y ; SI-CHECK: @fsub_v2f32 -; SI-CHECK: V_SUB_F32 -; SI-CHECK: V_SUB_F32 +; SI-CHECK: V_SUBREV_F32 +; SI-CHECK: V_SUBREV_F32 define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { entry: %0 = fsub <2 x float> %a, %b @@ -35,10 +35,10 @@ entry: ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} ; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} ; SI-CHECK: @fsub_v4f32 -; SI-CHECK: V_SUB_F32 -; SI-CHECK: V_SUB_F32 -; SI-CHECK: V_SUB_F32 -; SI-CHECK: V_SUB_F32 +; SI-CHECK: V_SUBREV_F32 +; SI-CHECK: V_SUBREV_F32 +; SI-CHECK: V_SUBREV_F32 +; SI-CHECK: V_SUBREV_F32 define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 %a = load <4 x float> addrspace(1) * %in diff --git a/test/CodeGen/R600/mul_uint24.ll b/test/CodeGen/R600/mul_uint24.ll index 419f2751b83..72bbe0f938a 100644 --- a/test/CodeGen/R600/mul_uint24.ll +++ b/test/CodeGen/R600/mul_uint24.ll @@ -23,7 +23,7 @@ entry: ; EG: BFE_INT {{[* ]*}}T{{[0-9]}}.{{[XYZW]}}, PV.[[MUL_CHAN]], 0.0, literal.x ; EG: 16 ; SI: V_MUL_U32_U24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; SI: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 16, +; SI: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 16 define void @i16_mul24(i32 addrspace(1)* %out, i16 %a, i16 %b) { entry: %0 = mul i16 %a, %b @@ -37,7 +37,7 @@ entry: ; The result must be sign-extended ; EG: BFE_INT {{[* ]*}}T{{[0-9]}}.{{[XYZW]}}, PV.[[MUL_CHAN]], 0.0, literal.x ; SI: V_MUL_U32_U24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} -; SI: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 8, +; SI: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 8 define void @i8_mul24(i32 addrspace(1)* %out, i8 %a, i8 %b) { entry: diff --git a/test/CodeGen/R600/vop-shrink.ll b/test/CodeGen/R600/vop-shrink.ll index f8bc2b4f78f..bf1aae4565e 100644 --- a/test/CodeGen/R600/vop-shrink.ll +++ b/test/CodeGen/R600/vop-shrink.ll @@ -1,9 +1,4 @@ ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; XXX: This testis for a bug in the SIShrinkInstruction pass and it will be -; relevant once we are selecting 64-bit instructions. We are -; currently selecting mostly 32-bit instruction, so the -; SIShrinkInstructions pass isn't doing much. -; XFAIL: * ; Test that we correctly commute a sub instruction ; FUNC-LABEL: @sub_rev -- 2.34.1