From 18fae69723ace3b430a7c9301e7f99d2ff01fadc Mon Sep 17 00:00:00 2001 From: Scott Michel Date: Tue, 25 Nov 2008 17:29:43 +0000 Subject: [PATCH] CellSPU: (a) Remove conditionally removed code in SelectXAddr. Basically, hope for the best that the A-form and D-form address predicates catch everything before the code decides to emit a X-form address. (b) Expand vector store test cases to include the usual suspects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60034 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/CellSPU/SPUISelDAGToDAG.cpp | 26 +-------- test/CodeGen/CellSPU/stores.ll | 77 ++++++++++++++++++++++++-- 2 files changed, 75 insertions(+), 28 deletions(-) diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index 159da4639f2..a2144d3e41b 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -591,33 +591,11 @@ SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base, SDValue &Index) { if (!SelectAFormAddr(Op, N, Base, Index) && !SelectDFormAddr(Op, N, Base, Index)) { -#if 0 - // Default form of a X-form address is r(r) in operands 0 and 1: - SDValue Op0 = N.getOperand(0); - SDValue Op1 = N.getOperand(1); - - if ((Op0.getOpcode() == ISD::Register - || Op.getOpcode() == ISD::CopyFromReg) - && (Op1.getOpcode() == ISD::Register - || Op.getOpcode() == ISD::CopyFromReg)) { - if (Op.getOpcode() == ISD::Register) - Base = Op0; - else - Base = Op0.getOperand(1); - - if (Op1.getOpcode() == ISD::Register) - Index = Op1; - else - Index = Op1.getOperand(1); - - return true; - } -#else - // All else fails, punt and use an X-form address: + // If the address is neither A-form or D-form, punt and use an X-form + // address: Base = N.getOperand(0); Index = N.getOperand(1); return true; -#endif } return false; diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll index b9534abfc1a..28d2e5b0a89 100644 --- a/test/CodeGen/CellSPU/stores.ll +++ b/test/CodeGen/CellSPU/stores.ll @@ -1,13 +1,75 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s -; RUN: grep {stqd.*0(\$3)} %t1.s | count 1 -; RUN: grep {stqd.*16(\$3)} %t1.s | count 1 -; RUN: grep 16256 %t1.s | count 1 -; RUN: grep 16384 %t1.s | count 1 +; RUN: grep {stqd.*0(\$3)} %t1.s | count 4 +; RUN: grep {stqd.*16(\$3)} %t1.s | count 4 +; RUN: grep 16256 %t1.s | count 2 +; RUN: grep 16384 %t1.s | count 1 +; RUN: grep {shli.*, 4} %t1.s | count 4 +; RUN: grep stqx %t1.s | count 4 ; ModuleID = 'stores.bc' target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" +define void @store_v16i8_1(<16 x i8>* %a) nounwind { +entry: + store <16 x i8> < i8 1, i8 2, i8 1, i8 1, i8 1, i8 2, i8 1, i8 1, i8 1, i8 2, i8 1, i8 1, i8 1, i8 2, i8 1, i8 1 >, <16 x i8>* %a + ret void +} + +define void @store_v16i8_2(<16 x i8>* %a) nounwind { +entry: + %arrayidx = getelementptr <16 x i8>* %a, i32 1 + store <16 x i8> < i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2 >, <16 x i8>* %arrayidx + ret void +} + +define void @store_v16i8_3(<16 x i8>* %a, i32 %i) nounwind { +entry: + %arrayidx = getelementptr <16 x i8>* %a, i32 %i + store <16 x i8> < i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1 >, <16 x i8>* %arrayidx + ret void +} + +define void @store_v8i16_1(<8 x i16>* %a) nounwind { +entry: + store <8 x i16> < i16 1, i16 2, i16 1, i16 1, i16 1, i16 2, i16 1, i16 1 >, <8 x i16>* %a + ret void +} + +define void @store_v8i16_2(<8 x i16>* %a) nounwind { +entry: + %arrayidx = getelementptr <8 x i16>* %a, i16 1 + store <8 x i16> < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2 >, <8 x i16>* %arrayidx + ret void +} + +define void @store_v8i16_3(<8 x i16>* %a, i32 %i) nounwind { +entry: + %arrayidx = getelementptr <8 x i16>* %a, i32 %i + store <8 x i16> < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 >, <8 x i16>* %arrayidx + ret void +} + +define void @store_v4i32_1(<4 x i32>* %a) nounwind { +entry: + store <4 x i32> < i32 1, i32 2, i32 1, i32 1 >, <4 x i32>* %a + ret void +} + +define void @store_v4i32_2(<4 x i32>* %a) nounwind { +entry: + %arrayidx = getelementptr <4 x i32>* %a, i32 1 + store <4 x i32> < i32 2, i32 2, i32 2, i32 2 >, <4 x i32>* %arrayidx + ret void +} + +define void @store_v4i32_3(<4 x i32>* %a, i32 %i) nounwind { +entry: + %arrayidx = getelementptr <4 x i32>* %a, i32 %i + store <4 x i32> < i32 1, i32 1, i32 1, i32 1 >, <4 x i32>* %arrayidx + ret void +} + define void @store_v4f32_1(<4 x float>* %a) nounwind { entry: store <4 x float> < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >, <4 x float>* %a @@ -20,3 +82,10 @@ entry: store <4 x float> < float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00 >, <4 x float>* %arrayidx ret void } + +define void @store_v4f32_3(<4 x float>* %a, i32 %i) nounwind { +entry: + %arrayidx = getelementptr <4 x float>* %a, i32 %i + store <4 x float> < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >, <4 x float>* %arrayidx + ret void +} -- 2.34.1