From 190144293db31aa2e5702091dd66da6690d02f3d Mon Sep 17 00:00:00 2001 From: "Vikram S. Adve" Date: Sat, 16 Mar 2002 21:42:33 +0000 Subject: [PATCH] Regression tests for live-variable analysis on machine code generated by llc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1882 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/LiveVar/Makefile | 18 ++++ test/LiveVar/loops.ll | 32 +++++++ test/LiveVar/loops.out | 202 ++++++++++++++++++++++++++++++++++++++++ test/LiveVar/phiuse.ll | 30 ++++++ test/LiveVar/phiuse.out | 143 ++++++++++++++++++++++++++++ 5 files changed, 425 insertions(+) create mode 100644 test/LiveVar/Makefile create mode 100644 test/LiveVar/loops.ll create mode 100644 test/LiveVar/loops.out create mode 100644 test/LiveVar/phiuse.ll create mode 100644 test/LiveVar/phiuse.out diff --git a/test/LiveVar/Makefile b/test/LiveVar/Makefile new file mode 100644 index 00000000000..fff15f22e7d --- /dev/null +++ b/test/LiveVar/Makefile @@ -0,0 +1,18 @@ +# test/Regression/Assembler/Makefile +# +# This directory contains regression tests for the LLVM assembler program. +# These LLVM source file tests are just required to assembler properly to pass. +# +LEVEL = ../../.. +include $(LEVEL)/test/Makefile.tests + +TESTS := $(wildcard *.ll) + +all:: $(addprefix Output/, $(TESTS:%.ll=%.out)) + +Output/%.out: %.ll $(LLC) Output/.dir + @echo "======== Testing live variables for $<" + $(LAS) < $< | $(LLC) -f -dlivevar i -o /dev/null 1> $@ 2>&1 + diff $@ . > /dev/null 2>& 1 || \ + ( rm -f $@; $(FAILURE) $@ ) + diff --git a/test/LiveVar/loops.ll b/test/LiveVar/loops.ll new file mode 100644 index 00000000000..4b521a2ce70 --- /dev/null +++ b/test/LiveVar/loops.ll @@ -0,0 +1,32 @@ +implementation + +;; Test live variable analysis: +;; -- a simple nested loop +;; -- a function call with arguments and return value + +int "LoopTest"(int %i, int %j) +begin +Start: + %j1 = add int 0, 0 + br label %L1Header + +L1Header: + %j2 = phi int [%j1, %Start], [%j3, %L2Done] + + %i1 = add int 0, 0 ; %i1 = 0 + br label %L2Body +L2Body: + %wl = phi int [%j, %L1Header], [%wl, %L2Body] ;; Useless PHI + %i2 = phi int [%i1, %L1Header], [%i3, %L2Body] + %i3 = add int %i2, 1 + %L2Done = seteq int %i3, 10 + br bool %L2Done, label %L2Done, label %L2Body +L2Done: + %j3 = add int %j2, %i3 + %L1Done = seteq int %j3, 100 + br bool %L1Done, label %L1Done, label %L1Header + +L1Done: + %recurse = call int %LoopTest(int %j3, int %j3) + ret int %recurse +end diff --git a/test/LiveVar/loops.out b/test/LiveVar/loops.out new file mode 100644 index 00000000000..7f94802727c --- /dev/null +++ b/test/LiveVar/loops.out @@ -0,0 +1,202 @@ +Analysing live variables ... + For BB 0x4c6560(L1Done) : + Defs: 0x4c65a8(recurse) 0x726cf8 + In: 0x4c6438(j3) + Out: + For BB 0x4c63f0(L2Done) : + Defs: 0x4c6438(j3) 0x4d8120 0x4ddf98 0x727280(PhiCp:) + In: 0x4d6478(i3) 0x5ab290(j2) + Out: + For BB 0x5ab450(L2Body) : + Defs: 0x4d6398(i2) 0x4d6478(i3) 0x5ab498(wl) 0x726f20 0x726ff8 0x7271c0 + In: 0x727388(PhiCp:) 0x727490(PhiCp:) + Out: + For BB 0x4d82a0(L1Header) : + Defs: 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:) 0x727490(PhiCp:) + In: 0x5414e0(j) 0x727280(PhiCp:) + Out: + For BB 0x501700(Start) : + Defs: 0x501748(j1) 0x727280(PhiCp:) + In: + Out: + + After Backward Pass 0... + For BB L1Done: + In: 0x4c6438(j3) + Out: + For BB L2Done: + In: 0x4d6478(i3) 0x5ab290(j2) + Out: 0x4c6438(j3) + For BB L2Body: + In: 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + Out: 0x4d6478(i3) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + For BB L1Header: + In: 0x5414e0(j) 0x727280(PhiCp:) + Out: 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + For BB Start: + In: 0x5414e0(j) + Out: 0x5414e0(j) 0x727280(PhiCp:) + + After Backward Pass 1... + For BB L1Done: + In: 0x4c6438(j3) + Out: + For BB L2Done: + In: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) + Out: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) + For BB L2Body: + In: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + Out: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + For BB L1Header: + In: 0x5414e0(j) 0x727280(PhiCp:) + Out: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + For BB Start: + In: 0x5414e0(j) + Out: 0x5414e0(j) 0x727280(PhiCp:) +Live Variable Analysis complete! + +======For BB Start: Live var sets for instructions====== + +Live var sets before/after instruction nop + Before: 0x5414e0(j) 0x727280(PhiCp:) + After : 0x5414e0(j) 0x727280(PhiCp:) + +Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header) + Before: 0x5414e0(j) 0x727280(PhiCp:) + After : 0x5414e0(j) 0x727280(PhiCp:) + +Live var sets before/after instruction add %reg(val j1) %reg(23) %reg(val PhiCp:)* + Before: 0x501748(j1) 0x5414e0(j) + After : 0x5414e0(j) 0x727280(PhiCp:) + +Live var sets before/after instruction add %reg(23) %reg(23) %reg(val j1)* + Before: 0x5414e0(j) + After : 0x501748(j1) 0x5414e0(j) + +======For BB L1Header: Live var sets for instructions====== + +Live var sets before/after instruction nop + Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + +Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L2Body) + Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + +Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val PhiCp:)* + Before: 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:) + After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + +Live var sets before/after instruction add %reg(val j) %reg(23) %reg(val PhiCp:)* + Before: 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) + After : 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:) + +Live var sets before/after instruction add %reg(23) %reg(23) %reg(val i1)* + Before: 0x5414e0(j) 0x5ab290(j2) + After : 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) + +Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val j2)* + Before: 0x5414e0(j) 0x727280(PhiCp:) + After : 0x5414e0(j) 0x5ab290(j2) + +======For BB L2Body: Live var sets for instructions====== + +Live var sets before/after instruction nop + Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + +Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L2Body) + Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + +Live var sets before/after instruction nop + Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + +Live var sets before/after instruction be %ccreg(val 0x726ff8) %disp(label L2Done) + Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) 0x727490(PhiCp:) + After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + +Live var sets before/after instruction add %reg(val i3) %reg(23) %reg(val PhiCp:)* + Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) + After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) 0x727490(PhiCp:) + +Live var sets before/after instruction add %reg(val wl) %reg(23) %reg(val PhiCp:)* + Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726ff8 + After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) + +Live var sets before/after instruction subcc %reg(val i3) %reg(val 0x7271c0) %reg(23)* %ccreg(val 0x726ff8)* + Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x7271c0 + After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726ff8 + +Live var sets before/after instruction setsw 10 %reg(val 0x7271c0)* + Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) + After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x7271c0 + +Live var sets before/after instruction add %reg(val i2) %reg(val 0x726f20) %reg(val i3)* + Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726f20 + After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) + +Live var sets before/after instruction setsw 1 %reg(val 0x726f20)* + Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) + After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726f20 + +Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val wl)* + Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) + After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) + +Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val i2)* + Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) + After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) + +======For BB L2Done: Live var sets for instructions====== + +Live var sets before/after instruction nop + Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) + After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) + +Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header) + Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) + After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) + +Live var sets before/after instruction nop + Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) + After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) + +Live var sets before/after instruction be %ccreg(val 0x4ddf98) %disp(label L1Done) + Before: 0x4c6438(j3) 0x4ddf98 0x5414e0(j) 0x727280(PhiCp:) + After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) + +Live var sets before/after instruction add %reg(val j3) %reg(23) %reg(val PhiCp:)* + Before: 0x4c6438(j3) 0x4ddf98 0x5414e0(j) + After : 0x4c6438(j3) 0x4ddf98 0x5414e0(j) 0x727280(PhiCp:) + +Live var sets before/after instruction subcc %reg(val j3) %reg(val 0x4d8120) %reg(23)* %ccreg(val 0x4ddf98)* + Before: 0x4c6438(j3) 0x4d8120 0x5414e0(j) + After : 0x4c6438(j3) 0x4ddf98 0x5414e0(j) + +Live var sets before/after instruction setsw 100 %reg(val 0x4d8120)* + Before: 0x4c6438(j3) 0x5414e0(j) + After : 0x4c6438(j3) 0x4d8120 0x5414e0(j) + +Live var sets before/after instruction add %reg(val j2) %reg(val i3) %reg(val j3)* + Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) + After : 0x4c6438(j3) 0x5414e0(j) + +======For BB L1Done: Live var sets for instructions====== + +Live var sets before/after instruction nop + Before: + After : + +Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x4c65a8 + Before: 0x4c65a8(recurse) + After : + +Live var sets before/after instruction nop + Before: 0x4c65a8(recurse) + After : 0x4c65a8(recurse) + +Live var sets before/after instruction call %disp(label LoopTest) Implicit:0x4c6438 0x4c6438 0x4c65a8* 0x726cf8* + Before: 0x4c6438(j3) + After : 0x4c65a8(recurse) diff --git a/test/LiveVar/phiuse.ll b/test/LiveVar/phiuse.ll new file mode 100644 index 00000000000..2e40e28b8f6 --- /dev/null +++ b/test/LiveVar/phiuse.ll @@ -0,0 +1,30 @@ +implementation + +;; Test live variable analysis: +;; -- phi argument is also used as first class value + +int "PhiTest"(int %i, int %j) +begin +Start: + %i1 = add int %i, %j + br label %L1Header + +L1Header: + %i2 = phi int [%i1, %Start], [%i4, %L1Header] + + %i3 = add int %i1, 0 + %i4 = add int %i2, %i3 + %L1Done = setgt int %i4, 10 + br bool %L1Done, label %L1Done, label %L1Header + +L1Done: + ret int %i4 +end + + +int "main"() +begin +bb0: + %result = call int %PhiTest( int 9, int 17 ) + ret int %result +end diff --git a/test/LiveVar/phiuse.out b/test/LiveVar/phiuse.out new file mode 100644 index 00000000000..985dce5be2e --- /dev/null +++ b/test/LiveVar/phiuse.out @@ -0,0 +1,143 @@ +Analysing live variables ... + For BB 0x4d6510(L1Done) : + Defs: + In: 0x4d6398(i4) + Out: + For BB 0x5ab408(L1Header) : + Defs: 0x4c6528 0x4d6350(i3) 0x4d6398(i4) 0x4ddf50 0x5ab450(i2) + In: 0x4d8290(i1) 0x726c68(PhiCp:) + Out: + For BB 0x4d8248(Start) : + Defs: 0x4d8290(i1) 0x726c68(PhiCp:) + In: 0x4e4690(j) 0x501658(i) + Out: + + After Backward Pass 0... + For BB L1Done: + In: 0x4d6398(i4) + Out: + For BB L1Header: + In: 0x4d8290(i1) 0x726c68(PhiCp:) + Out: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) + For BB Start: + In: 0x4e4690(j) 0x501658(i) + Out: 0x4d8290(i1) 0x726c68(PhiCp:) + + After Backward Pass 1... + For BB L1Done: + In: 0x4d6398(i4) + Out: + For BB L1Header: + In: 0x4d8290(i1) 0x726c68(PhiCp:) + Out: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) + For BB Start: + In: 0x4e4690(j) 0x501658(i) + Out: 0x4d8290(i1) 0x726c68(PhiCp:) +Live Variable Analysis complete! + +======For BB Start: Live var sets for instructions====== + +Live var sets before/after instruction nop + Before: 0x4d8290(i1) 0x726c68(PhiCp:) + After : 0x4d8290(i1) 0x726c68(PhiCp:) + +Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header) + Before: 0x4d8290(i1) 0x726c68(PhiCp:) + After : 0x4d8290(i1) 0x726c68(PhiCp:) + +Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val PhiCp:)* + Before: 0x4d8290(i1) + After : 0x4d8290(i1) 0x726c68(PhiCp:) + +Live var sets before/after instruction add %reg(val i) %reg(val j) %reg(val i1)* + Before: 0x4e4690(j) 0x501658(i) + After : 0x4d8290(i1) + +======For BB L1Header: Live var sets for instructions====== + +Live var sets before/after instruction nop + Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) + After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) + +Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header) + Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) + After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) + +Live var sets before/after instruction nop + Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) + After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) + +Live var sets before/after instruction bg %ccreg(val 0x4ddf50) %disp(label L1Done) + Before: 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 0x726c68(PhiCp:) + After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) + +Live var sets before/after instruction add %reg(val i4) %reg(23) %reg(val PhiCp:)* + Before: 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 + After : 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 0x726c68(PhiCp:) + +Live var sets before/after instruction subcc %reg(val i4) %reg(val 0x4c6528) %reg(23)* %ccreg(val 0x4ddf50)* + Before: 0x4c6528 0x4d6398(i4) 0x4d8290(i1) + After : 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 + +Live var sets before/after instruction setsw 10 %reg(val 0x4c6528)* + Before: 0x4d6398(i4) 0x4d8290(i1) + After : 0x4c6528 0x4d6398(i4) 0x4d8290(i1) + +Live var sets before/after instruction add %reg(val i2) %reg(val i3) %reg(val i4)* + Before: 0x4d6350(i3) 0x4d8290(i1) 0x5ab450(i2) + After : 0x4d6398(i4) 0x4d8290(i1) + +Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val i3)* + Before: 0x4d8290(i1) 0x5ab450(i2) + After : 0x4d6350(i3) 0x4d8290(i1) 0x5ab450(i2) + +Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val i2)* + Before: 0x4d8290(i1) 0x726c68(PhiCp:) + After : 0x4d8290(i1) 0x5ab450(i2) + +======For BB L1Done: Live var sets for instructions====== + +Live var sets before/after instruction nop + Before: + After : + +Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x4d6398 + Before: 0x4d6398(i4) + After : +Analysing live variables ... + For BB 0x5ab498(bb0) : + Defs: 0x4daa90 0x4f2d68 0x4f2df8 0x501768(result) + In: + Out: + + After Backward Pass 0... + For BB bb0: + In: + Out: +Live Variable Analysis complete! + +======For BB bb0: Live var sets for instructions====== + +Live var sets before/after instruction nop + Before: + After : + +Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x501768 + Before: 0x501768(result) + After : + +Live var sets before/after instruction nop + Before: 0x501768(result) + After : 0x501768(result) + +Live var sets before/after instruction call %disp(label PhiTest) Implicit:0x4f2d68 0x4f2df8 0x501768* 0x4daa90* + Before: 0x4f2d68 0x4f2df8 + After : 0x501768(result) + +Live var sets before/after instruction setsw 17 %reg(val 0x4f2df8)* + Before: 0x4f2d68 + After : 0x4f2d68 0x4f2df8 + +Live var sets before/after instruction setsw 9 %reg(val 0x4f2d68)* + Before: + After : 0x4f2d68 -- 2.34.1