From 1937233a222144826216aad1eb18ccbbd2ea3ecd Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Sat, 31 Jan 2015 11:17:59 +0000 Subject: [PATCH] [PM] Switch the TargetMachine interface from accepting a pass manager base which it adds a single analysis pass to, to instead return the type erased TargetTransformInfo object constructed for that TargetMachine. This removes all of the pass variants for TTI. There is now a single TTI *pass* in the Analysis layer. All of the Analysis <-> Target communication is through the TTI's type erased interface itself. While the diff is large here, it is nothing more that code motion to make types available in a header file for use in a different source file within each target. I've tried to keep all the doxygen comments and file boilerplate in line with this move, but let me know if I missed anything. With this in place, the next step to making TTI work with the new pass manager is to introduce a really simple new-style analysis that produces a TTI object via a callback into this routine on the target machine. Once we have that, we'll have the building blocks necessary to accept a function argument as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227685 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Analysis/TargetTransformInfo.h | 16 +- include/llvm/CodeGen/BasicTTIImpl.h | 24 +++ include/llvm/Target/TargetMachine.h | 17 ++- lib/Analysis/TargetTransformInfo.cpp | 30 ++-- lib/CodeGen/BasicTargetTransformInfo.cpp | 42 +----- lib/CodeGen/LLVMTargetMachine.cpp | 7 +- lib/LTO/LTOCodeGenerator.cpp | 3 +- lib/Target/AArch64/AArch64TargetMachine.cpp | 5 +- lib/Target/AArch64/AArch64TargetMachine.h | 2 +- .../AArch64/AArch64TargetTransformInfo.cpp | 130 +--------------- .../AArch64/AArch64TargetTransformInfo.h | 140 ++++++++++++++++++ lib/Target/ARM/ARMTargetMachine.cpp | 5 +- lib/Target/ARM/ARMTargetMachine.h | 2 +- lib/Target/ARM/ARMTargetTransformInfo.cpp | 123 +-------------- lib/Target/ARM/ARMTargetTransformInfo.h | 129 ++++++++++++++++ lib/Target/Mips/MipsTargetMachine.cpp | 11 +- lib/Target/Mips/MipsTargetMachine.h | 2 +- lib/Target/NVPTX/NVPTXTargetMachine.cpp | 5 +- lib/Target/NVPTX/NVPTXTargetMachine.h | 3 +- lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp | 58 +------- lib/Target/NVPTX/NVPTXTargetTransformInfo.h | 67 +++++++++ lib/Target/PowerPC/PPCTargetMachine.cpp | 5 +- lib/Target/PowerPC/PPCTargetMachine.h | 4 +- lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 92 +----------- lib/Target/PowerPC/PPCTargetTransformInfo.h | 100 +++++++++++++ lib/Target/R600/AMDGPUTargetMachine.cpp | 7 +- lib/Target/R600/AMDGPUTargetMachine.h | 4 +- lib/Target/R600/AMDGPUTargetTransformInfo.cpp | 53 +------ lib/Target/R600/AMDGPUTargetTransformInfo.h | 71 +++++++++ lib/Target/TargetMachine.cpp | 4 +- lib/Target/TargetMachineC.cpp | 3 +- lib/Target/X86/X86TargetMachine.cpp | 7 +- lib/Target/X86/X86TargetMachine.h | 3 +- lib/Target/X86/X86TargetTransformInfo.cpp | 92 +----------- lib/Target/X86/X86TargetTransformInfo.h | 110 ++++++++++++++ lib/Target/XCore/CMakeLists.txt | 1 - lib/Target/XCore/XCoreTargetMachine.cpp | 5 +- lib/Target/XCore/XCoreTargetMachine.h | 2 +- ...ormInfo.cpp => XCoreTargetTransformInfo.h} | 29 ++-- tools/opt/opt.cpp | 13 +- 40 files changed, 761 insertions(+), 665 deletions(-) create mode 100644 lib/Target/AArch64/AArch64TargetTransformInfo.h create mode 100644 lib/Target/ARM/ARMTargetTransformInfo.h create mode 100644 lib/Target/NVPTX/NVPTXTargetTransformInfo.h create mode 100644 lib/Target/PowerPC/PPCTargetTransformInfo.h create mode 100644 lib/Target/R600/AMDGPUTargetTransformInfo.h create mode 100644 lib/Target/X86/X86TargetTransformInfo.h rename lib/Target/XCore/{XCoreTargetTransformInfo.cpp => XCoreTargetTransformInfo.h} (69%) diff --git a/include/llvm/Analysis/TargetTransformInfo.h b/include/llvm/Analysis/TargetTransformInfo.h index b0811ab5c15..20bc70dfd66 100644 --- a/include/llvm/Analysis/TargetTransformInfo.h +++ b/include/llvm/Analysis/TargetTransformInfo.h @@ -61,6 +61,13 @@ public: /// implementaion that encodes appropriate costs for their target. template TargetTransformInfo(T Impl); + /// \brief Construct a baseline TTI object using a minimal implementation of + /// the \c Concept API below. + /// + /// The TTI implementation will reflect the information in the DataLayout + /// provided if non-null. + explicit TargetTransformInfo(const DataLayout *DL); + // Provide move semantics. TargetTransformInfo(TargetTransformInfo &&Arg); TargetTransformInfo &operator=(TargetTransformInfo &&RHS); @@ -723,12 +730,11 @@ public: const TargetTransformInfo &getTTI() const { return TTI; } }; -/// \brief Create the base case instance of a pass in the TTI analysis group. +/// \brief Create an analysis pass wrapper around a TTI object. /// -/// This class provides the base case for the stack of TTI analyzes. It doesn't -/// delegate to anything and uses the STTI and VTTI objects passed in to -/// satisfy the queries. -ImmutablePass *createNoTargetTransformInfoPass(const DataLayout *DL); +/// This analysis pass just holds the TTI instance and makes it available to +/// clients. +ImmutablePass *createTargetTransformInfoWrapperPass(TargetTransformInfo TTI); } // End llvm namespace diff --git a/include/llvm/CodeGen/BasicTTIImpl.h b/include/llvm/CodeGen/BasicTTIImpl.h index 7d0aeb4f84b..7fd16e1de54 100644 --- a/include/llvm/CodeGen/BasicTTIImpl.h +++ b/include/llvm/CodeGen/BasicTTIImpl.h @@ -621,6 +621,30 @@ public: /// @} }; + +/// \brief Concrete BasicTTIImpl that can be used if no further customization +/// is needed. +class BasicTTIImpl : public BasicTTIImplBase { + typedef BasicTTIImplBase BaseT; + +public: + explicit BasicTTIImpl(const TargetMachine *TM = nullptr); + + // Provide value semantics. MSVC requires that we spell all of these out. + BasicTTIImpl(const BasicTTIImpl &Arg) + : BaseT(static_cast(Arg)) {} + BasicTTIImpl(BasicTTIImpl &&Arg) + : BaseT(std::move(static_cast(Arg))) {} + BasicTTIImpl &operator=(const BasicTTIImpl &RHS) { + BaseT::operator=(static_cast(RHS)); + return *this; + } + BasicTTIImpl &operator=(BasicTTIImpl &&RHS) { + BaseT::operator=(std::move(static_cast(RHS))); + return *this; + } +}; + } #endif diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index 0e3997c49b3..109985abb1e 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -40,6 +40,7 @@ class TargetPassConfig; class TargetRegisterInfo; class TargetSelectionDAGInfo; class TargetSubtargetInfo; +class TargetTransformInfo; class formatted_raw_ostream; class raw_ostream; class TargetLoweringObjectFile; @@ -186,8 +187,12 @@ public: /// sections. void setFunctionSections(bool); - /// \brief Register analysis passes for this target with a pass manager. - virtual void addAnalysisPasses(PassManagerBase &); + /// \brief Get a TTI implementation for the target. + /// + /// Targets should override this method to provide target-accurate + /// information to the mid-level optimizer. If left with the baseline only + /// a very conservative set of heuristics will be used. + virtual TargetTransformInfo getTTI(); /// CodeGenFileType - These enums are meant to be passed into /// addPassesToEmitFile to indicate what type of file to emit, and returned by @@ -240,10 +245,12 @@ protected: // Can only create subclasses. void initAsmInfo(); public: - /// \brief Register analysis passes for this target with a pass manager. + /// \brief Get a TTI implementation for the target. /// - /// This registers target independent analysis passes. - void addAnalysisPasses(PassManagerBase &PM) override; + /// This uses the common code generator to produce a TTI implementation. + /// Targets may override it to provide more customized TTI implementation + /// instead. + TargetTransformInfo getTTI() override; /// createPassConfig - Create a pass configuration object to be used by /// addPassToEmitX methods for generating a pipeline of CodeGen passes. diff --git a/lib/Analysis/TargetTransformInfo.cpp b/lib/Analysis/TargetTransformInfo.cpp index cdbce0d78c1..a78d1db396a 100644 --- a/lib/Analysis/TargetTransformInfo.cpp +++ b/lib/Analysis/TargetTransformInfo.cpp @@ -21,6 +21,20 @@ using namespace llvm; #define DEBUG_TYPE "tti" +namespace { +/// \brief No-op implementation of the TTI interface using the utility base +/// classes. +/// +/// This is used when no target specific information is available. +struct NoTTIImpl : TargetTransformInfoImplCRTPBase { + explicit NoTTIImpl(const DataLayout *DL) + : TargetTransformInfoImplCRTPBase(DL) {} +}; +} + +TargetTransformInfo::TargetTransformInfo(const DataLayout *DL) + : TTIImpl(new Model(NoTTIImpl(DL))) {} + TargetTransformInfo::~TargetTransformInfo() {} TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg) @@ -241,17 +255,6 @@ Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic( TargetTransformInfo::Concept::~Concept() {} -namespace { -/// \brief No-op implementation of the TTI interface using the utility base -/// classes. -/// -/// This is used when no target specific information is available. -struct NoTTIImpl : TargetTransformInfoImplCRTPBase { - explicit NoTTIImpl(const DataLayout *DL) - : TargetTransformInfoImplCRTPBase(DL) {} -}; -} - // Register the basic pass. INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti", "Target Transform Information", false, true) @@ -272,6 +275,7 @@ TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass( *PassRegistry::getPassRegistry()); } -ImmutablePass *llvm::createNoTargetTransformInfoPass(const DataLayout *DL) { - return new TargetTransformInfoWrapperPass(NoTTIImpl(DL)); +ImmutablePass * +llvm::createTargetTransformInfoWrapperPass(TargetTransformInfo TTI) { + return new TargetTransformInfoWrapperPass(std::move(TTI)); } diff --git a/lib/CodeGen/BasicTargetTransformInfo.cpp b/lib/CodeGen/BasicTargetTransformInfo.cpp index 5cd0ed3bba1..a9fe43c6605 100644 --- a/lib/CodeGen/BasicTargetTransformInfo.cpp +++ b/lib/CodeGen/BasicTargetTransformInfo.cpp @@ -24,45 +24,13 @@ #include using namespace llvm; +#define DEBUG_TYPE "basictti" + +// This flag is used by the template base class for BasicTTIImpl, and here to +// provide a definition. cl::opt llvm::PartialUnrollingThreshold("partial-unrolling-threshold", cl::init(0), cl::desc("Threshold for partial unrolling"), cl::Hidden); -#define DEBUG_TYPE "basictti" - -namespace { -class BasicTTIImpl : public BasicTTIImplBase { - typedef BasicTTIImplBase BaseT; - -public: - explicit BasicTTIImpl(const TargetMachine *TM = nullptr) : BaseT(TM) {} - - // Provide value semantics. MSVC requires that we spell all of these out. - BasicTTIImpl(const BasicTTIImpl &Arg) - : BaseT(static_cast(Arg)) {} - BasicTTIImpl(BasicTTIImpl &&Arg) - : BaseT(std::move(static_cast(Arg))) {} - BasicTTIImpl &operator=(const BasicTTIImpl &RHS) { - BaseT::operator=(static_cast(RHS)); - return *this; - } - BasicTTIImpl &operator=(BasicTTIImpl &&RHS) { - BaseT::operator=(std::move(static_cast(RHS))); - return *this; - } -}; -} - -ImmutablePass * -llvm::createBasicTargetTransformInfoPass(const TargetMachine *TM) { - return new TargetTransformInfoWrapperPass(BasicTTIImpl(TM)); -} - - -//===----------------------------------------------------------------------===// -// -// Calls used by the vectorizers. -// -//===----------------------------------------------------------------------===// - +BasicTTIImpl::BasicTTIImpl(const TargetMachine *TM) : BaseT(TM) {} diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index ae21489d5e6..f7377c858f3 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -15,6 +15,7 @@ #include "llvm/Analysis/JumpInstrTableInfo.h" #include "llvm/Analysis/Passes.h" #include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/CodeGen/BasicTTIImpl.h" #include "llvm/CodeGen/ForwardControlFlowIntegrity.h" #include "llvm/CodeGen/JumpInstrTables.h" #include "llvm/CodeGen/MachineFunctionAnalysis.h" @@ -77,8 +78,8 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL); } -void LLVMTargetMachine::addAnalysisPasses(PassManagerBase &PM) { - PM.add(createBasicTargetTransformInfoPass(this)); +TargetTransformInfo LLVMTargetMachine::getTTI() { + return TargetTransformInfo(BasicTTIImpl(this)); } /// addPassesToX helper drives creation and initialization of TargetPassConfig. @@ -89,7 +90,7 @@ static MCContext *addPassesToGenerateCode(LLVMTargetMachine *TM, AnalysisID StopAfter) { // Add internal analysis passes from the target machine. - TM->addAnalysisPasses(PM); + PM.add(createTargetTransformInfoWrapperPass(TM->getTTI())); // Targets may override createPassConfig to provide a target-specific // subclass. diff --git a/lib/LTO/LTOCodeGenerator.cpp b/lib/LTO/LTOCodeGenerator.cpp index e0fcdec8ad0..feea6570a31 100644 --- a/lib/LTO/LTOCodeGenerator.cpp +++ b/lib/LTO/LTOCodeGenerator.cpp @@ -16,6 +16,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/Analysis/Passes.h" #include "llvm/Analysis/TargetLibraryInfo.h" +#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Bitcode/ReaderWriter.h" #include "llvm/CodeGen/RuntimeLibcalls.h" #include "llvm/Config/config.h" @@ -489,7 +490,7 @@ bool LTOCodeGenerator::generateObjectFile(raw_ostream &out, mergedModule->setDataLayout(TargetMach->getDataLayout()); passes.add(new DataLayoutPass()); - TargetMach->addAnalysisPasses(passes); + passes.add(createTargetTransformInfoWrapperPass(TargetMach->getTTI())); Triple TargetTriple(TargetMach->getTargetTriple()); PassManagerBuilder PMB; diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp index a0d1b844a29..bbd85ea723c 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -13,6 +13,7 @@ #include "AArch64.h" #include "AArch64TargetMachine.h" #include "AArch64TargetObjectFile.h" +#include "AArch64TargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/IR/Function.h" @@ -195,8 +196,8 @@ public: }; } // namespace -void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) { - PM.add(createAArch64TargetTransformInfoPass(this)); +TargetTransformInfo AArch64TargetMachine::getTTI() { + return TargetTransformInfo(AArch64TTIImpl(this)); } TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) { diff --git a/lib/Target/AArch64/AArch64TargetMachine.h b/lib/Target/AArch64/AArch64TargetMachine.h index 983d885e86f..6ed3bb4a35d 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.h +++ b/lib/Target/AArch64/AArch64TargetMachine.h @@ -46,7 +46,7 @@ public: TargetPassConfig *createPassConfig(PassManagerBase &PM) override; /// \brief Register AArch64 analysis passes with a pass manager. - void addAnalysisPasses(PassManagerBase &PM) override; + TargetTransformInfo getTTI() override; TargetLoweringObjectFile* getObjFileLowering() const override { return TLOF.get(); diff --git a/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index f1e9c6adb53..eab080bb24c 100644 --- a/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -1,4 +1,4 @@ -//===-- AArch64TargetTransformInfo.cpp - AArch64 specific TTI pass --------===// +//===-- AArch64TargetTransformInfo.cpp - AArch64 specific TTI -------------===// // // The LLVM Compiler Infrastructure // @@ -6,16 +6,8 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -/// \file -/// This file implements a TargetTransformInfo analysis pass specific to the -/// AArch64 target machine. It uses the target's detailed information to provide -/// more precise answers to certain TTI queries, while letting the target -/// independent and default TTI implementations handle the rest. -/// -//===----------------------------------------------------------------------===// -#include "AArch64.h" -#include "AArch64TargetMachine.h" +#include "AArch64TargetTransformInfo.h" #include "MCTargetDesc/AArch64AddressingModes.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/BasicTTIImpl.h" @@ -27,124 +19,6 @@ using namespace llvm; #define DEBUG_TYPE "aarch64tti" -namespace { - -class AArch64TTIImpl : public BasicTTIImplBase { - typedef BasicTTIImplBase BaseT; - typedef TargetTransformInfo TTI; - - const AArch64Subtarget *ST; - const AArch64TargetLowering *TLI; - - /// Estimate the overhead of scalarizing an instruction. Insert and Extract - /// are set if the result needs to be inserted and/or extracted from vectors. - unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract); - - enum MemIntrinsicType { - VECTOR_LDST_TWO_ELEMENTS, - VECTOR_LDST_THREE_ELEMENTS, - VECTOR_LDST_FOUR_ELEMENTS - }; - -public: - explicit AArch64TTIImpl(const AArch64TargetMachine *TM = nullptr) - : BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr), - TLI(ST ? ST->getTargetLowering() : nullptr) {} - - // Provide value semantics. MSVC requires that we spell all of these out. - AArch64TTIImpl(const AArch64TTIImpl &Arg) - : BaseT(static_cast(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} - AArch64TTIImpl(AArch64TTIImpl &&Arg) - : BaseT(std::move(static_cast(Arg))), ST(std::move(Arg.ST)), - TLI(std::move(Arg.TLI)) {} - AArch64TTIImpl &operator=(const AArch64TTIImpl &RHS) { - BaseT::operator=(static_cast(RHS)); - ST = RHS.ST; - TLI = RHS.TLI; - return *this; - } - AArch64TTIImpl &operator=(AArch64TTIImpl &&RHS) { - BaseT::operator=(std::move(static_cast(RHS))); - ST = std::move(RHS.ST); - TLI = std::move(RHS.TLI); - return *this; - } - - /// \name Scalar TTI Implementations - /// @{ - - using BaseT::getIntImmCost; - unsigned getIntImmCost(int64_t Val); - unsigned getIntImmCost(const APInt &Imm, Type *Ty); - unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, - Type *Ty); - unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, - Type *Ty); - TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth); - - /// @} - - /// \name Vector TTI Implementations - /// @{ - - unsigned getNumberOfRegisters(bool Vector) { - if (Vector) { - if (ST->hasNEON()) - return 32; - return 0; - } - return 31; - } - - unsigned getRegisterBitWidth(bool Vector) { - if (Vector) { - if (ST->hasNEON()) - return 128; - return 0; - } - return 64; - } - - unsigned getMaxInterleaveFactor(); - - unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src); - - unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); - - unsigned getArithmeticInstrCost( - unsigned Opcode, Type *Ty, - TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, - TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, - TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, - TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None); - - unsigned getAddressComputationCost(Type *Ty, bool IsComplex); - - unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy); - - unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, - unsigned AddressSpace); - - unsigned getCostOfKeepingLiveOverCall(ArrayRef Tys); - - void getUnrollingPreferences(const Function *F, Loop *L, - TTI::UnrollingPreferences &UP); - - Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, - Type *ExpectedType); - - bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info); - - /// @} -}; - -} // end anonymous namespace - -ImmutablePass * -llvm::createAArch64TargetTransformInfoPass(const AArch64TargetMachine *TM) { - return new TargetTransformInfoWrapperPass(AArch64TTIImpl(TM)); -} - /// \brief Calculate the cost of materializing a 64-bit value. This helper /// method might only calculate a fraction of a larger immediate. Therefore it /// is valid to return a cost of ZERO. diff --git a/lib/Target/AArch64/AArch64TargetTransformInfo.h b/lib/Target/AArch64/AArch64TargetTransformInfo.h new file mode 100644 index 00000000000..30a2c23fd36 --- /dev/null +++ b/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -0,0 +1,140 @@ +//===-- AArch64TargetTransformInfo.h - AArch64 specific TTI -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// \file +/// This file a TargetTransformInfo::Concept conforming object specific to the +/// AArch64 target machine. It uses the target's detailed information to +/// provide more precise answers to certain TTI queries, while letting the +/// target independent and default TTI implementations handle the rest. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H +#define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H + +#include "AArch64.h" +#include "AArch64TargetMachine.h" +#include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/BasicTTIImpl.h" +#include "llvm/Target/TargetLowering.h" +#include + +namespace llvm { + +class AArch64TTIImpl : public BasicTTIImplBase { + typedef BasicTTIImplBase BaseT; + typedef TargetTransformInfo TTI; + + const AArch64Subtarget *ST; + const AArch64TargetLowering *TLI; + + /// Estimate the overhead of scalarizing an instruction. Insert and Extract + /// are set if the result needs to be inserted and/or extracted from vectors. + unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract); + + enum MemIntrinsicType { + VECTOR_LDST_TWO_ELEMENTS, + VECTOR_LDST_THREE_ELEMENTS, + VECTOR_LDST_FOUR_ELEMENTS + }; + +public: + explicit AArch64TTIImpl(const AArch64TargetMachine *TM = nullptr) + : BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr), + TLI(ST ? ST->getTargetLowering() : nullptr) {} + + // Provide value semantics. MSVC requires that we spell all of these out. + AArch64TTIImpl(const AArch64TTIImpl &Arg) + : BaseT(static_cast(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} + AArch64TTIImpl(AArch64TTIImpl &&Arg) + : BaseT(std::move(static_cast(Arg))), ST(std::move(Arg.ST)), + TLI(std::move(Arg.TLI)) {} + AArch64TTIImpl &operator=(const AArch64TTIImpl &RHS) { + BaseT::operator=(static_cast(RHS)); + ST = RHS.ST; + TLI = RHS.TLI; + return *this; + } + AArch64TTIImpl &operator=(AArch64TTIImpl &&RHS) { + BaseT::operator=(std::move(static_cast(RHS))); + ST = std::move(RHS.ST); + TLI = std::move(RHS.TLI); + return *this; + } + + /// \name Scalar TTI Implementations + /// @{ + + using BaseT::getIntImmCost; + unsigned getIntImmCost(int64_t Val); + unsigned getIntImmCost(const APInt &Imm, Type *Ty); + unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, + Type *Ty); + unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, + Type *Ty); + TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth); + + /// @} + + /// \name Vector TTI Implementations + /// @{ + + unsigned getNumberOfRegisters(bool Vector) { + if (Vector) { + if (ST->hasNEON()) + return 32; + return 0; + } + return 31; + } + + unsigned getRegisterBitWidth(bool Vector) { + if (Vector) { + if (ST->hasNEON()) + return 128; + return 0; + } + return 64; + } + + unsigned getMaxInterleaveFactor(); + + unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src); + + unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); + + unsigned getArithmeticInstrCost( + unsigned Opcode, Type *Ty, + TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, + TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, + TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, + TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None); + + unsigned getAddressComputationCost(Type *Ty, bool IsComplex); + + unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy); + + unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, + unsigned AddressSpace); + + unsigned getCostOfKeepingLiveOverCall(ArrayRef Tys); + + void getUnrollingPreferences(const Function *F, Loop *L, + TTI::UnrollingPreferences &UP); + + Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, + Type *ExpectedType); + + bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info); + + /// @} +}; + +} // end namespace llvm + +#endif diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 3f919147904..008b4773c6d 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -14,6 +14,7 @@ #include "ARMFrameLowering.h" #include "ARMTargetMachine.h" #include "ARMTargetObjectFile.h" +#include "ARMTargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/IR/Function.h" #include "llvm/MC/MCAsmInfo.h" @@ -215,8 +216,8 @@ ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const { return I.get(); } -void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) { - PM.add(createARMTargetTransformInfoPass(this)); +TargetTransformInfo ARMBaseTargetMachine::getTTI() { + return TargetTransformInfo(ARMTTIImpl(this)); } diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h index 31e316a646e..0a15d1765c2 100644 --- a/lib/Target/ARM/ARMTargetMachine.h +++ b/lib/Target/ARM/ARMTargetMachine.h @@ -50,7 +50,7 @@ public: const DataLayout *getDataLayout() const override { return &DL; } /// \brief Register ARM analysis passes with a pass manager. - void addAnalysisPasses(PassManagerBase &PM) override; + TargetTransformInfo getTTI() override; // Pass Pipeline Configuration TargetPassConfig *createPassConfig(PassManagerBase &PM) override; diff --git a/lib/Target/ARM/ARMTargetTransformInfo.cpp b/lib/Target/ARM/ARMTargetTransformInfo.cpp index b03fa3a21d4..1cb1efb1924 100644 --- a/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -1,4 +1,4 @@ -//===-- ARMTargetTransformInfo.cpp - ARM specific TTI pass ----------------===// +//===-- ARMTargetTransformInfo.cpp - ARM specific TTI ---------------------===// // // The LLVM Compiler Infrastructure // @@ -6,18 +6,8 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -/// \file -/// This file implements a TargetTransformInfo analysis pass specific to the -/// ARM target machine. It uses the target's detailed information to provide -/// more precise answers to certain TTI queries, while letting the target -/// independent and default TTI implementations handle the rest. -/// -//===----------------------------------------------------------------------===// -#include "ARM.h" -#include "ARMTargetMachine.h" -#include "llvm/Analysis/TargetTransformInfo.h" -#include "llvm/CodeGen/BasicTTIImpl.h" +#include "ARMTargetTransformInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Target/CostTable.h" #include "llvm/Target/TargetLowering.h" @@ -25,115 +15,6 @@ using namespace llvm; #define DEBUG_TYPE "armtti" -namespace { - -class ARMTTIImpl : public BasicTTIImplBase { - typedef BasicTTIImplBase BaseT; - typedef TargetTransformInfo TTI; - - const ARMSubtarget *ST; - const ARMTargetLowering *TLI; - - /// Estimate the overhead of scalarizing an instruction. Insert and Extract - /// are set if the result needs to be inserted and/or extracted from vectors. - unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract); - -public: - explicit ARMTTIImpl(const ARMBaseTargetMachine *TM = nullptr) - : BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr), - TLI(ST ? ST->getTargetLowering() : nullptr) {} - - // Provide value semantics. MSVC requires that we spell all of these out. - ARMTTIImpl(const ARMTTIImpl &Arg) - : BaseT(static_cast(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} - ARMTTIImpl(ARMTTIImpl &&Arg) - : BaseT(std::move(static_cast(Arg))), ST(std::move(Arg.ST)), - TLI(std::move(Arg.TLI)) {} - ARMTTIImpl &operator=(const ARMTTIImpl &RHS) { - BaseT::operator=(static_cast(RHS)); - ST = RHS.ST; - TLI = RHS.TLI; - return *this; - } - ARMTTIImpl &operator=(ARMTTIImpl &&RHS) { - BaseT::operator=(std::move(static_cast(RHS))); - ST = std::move(RHS.ST); - TLI = std::move(RHS.TLI); - return *this; - } - - /// \name Scalar TTI Implementations - /// @{ - - using BaseT::getIntImmCost; - unsigned getIntImmCost(const APInt &Imm, Type *Ty); - - /// @} - - - /// \name Vector TTI Implementations - /// @{ - - unsigned getNumberOfRegisters(bool Vector) { - if (Vector) { - if (ST->hasNEON()) - return 16; - return 0; - } - - if (ST->isThumb1Only()) - return 8; - return 13; - } - - unsigned getRegisterBitWidth(bool Vector) { - if (Vector) { - if (ST->hasNEON()) - return 128; - return 0; - } - - return 32; - } - - unsigned getMaxInterleaveFactor() { - // These are out of order CPUs: - if (ST->isCortexA15() || ST->isSwift()) - return 2; - return 1; - } - - unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, - Type *SubTp); - - unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src); - - unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy); - - unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); - - unsigned getAddressComputationCost(Type *Val, bool IsComplex); - - unsigned getArithmeticInstrCost( - unsigned Opcode, Type *Ty, - TTI::OperandValueKind Op1Info = TTI::OK_AnyValue, - TTI::OperandValueKind Op2Info = TTI::OK_AnyValue, - TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, - TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None); - - unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, - unsigned AddressSpace); - - /// @} -}; - -} // end anonymous namespace - -ImmutablePass * -llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) { - return new TargetTransformInfoWrapperPass(ARMTTIImpl(TM)); -} - unsigned ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { assert(Ty->isIntegerTy()); diff --git a/lib/Target/ARM/ARMTargetTransformInfo.h b/lib/Target/ARM/ARMTargetTransformInfo.h new file mode 100644 index 00000000000..8f7c3b43352 --- /dev/null +++ b/lib/Target/ARM/ARMTargetTransformInfo.h @@ -0,0 +1,129 @@ +//===-- ARMTargetTransformInfo.h - ARM specific TTI -------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// \file +/// This file a TargetTransformInfo::Concept conforming object specific to the +/// ARM target machine. It uses the target's detailed information to +/// provide more precise answers to certain TTI queries, while letting the +/// target independent and default TTI implementations handle the rest. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H +#define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H + +#include "ARM.h" +#include "ARMTargetMachine.h" +#include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/BasicTTIImpl.h" +#include "llvm/Target/TargetLowering.h" + +namespace llvm { + +class ARMTTIImpl : public BasicTTIImplBase { + typedef BasicTTIImplBase BaseT; + typedef TargetTransformInfo TTI; + + const ARMSubtarget *ST; + const ARMTargetLowering *TLI; + + /// Estimate the overhead of scalarizing an instruction. Insert and Extract + /// are set if the result needs to be inserted and/or extracted from vectors. + unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract); + +public: + explicit ARMTTIImpl(const ARMBaseTargetMachine *TM = nullptr) + : BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr), + TLI(ST ? ST->getTargetLowering() : nullptr) {} + + // Provide value semantics. MSVC requires that we spell all of these out. + ARMTTIImpl(const ARMTTIImpl &Arg) + : BaseT(static_cast(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} + ARMTTIImpl(ARMTTIImpl &&Arg) + : BaseT(std::move(static_cast(Arg))), ST(std::move(Arg.ST)), + TLI(std::move(Arg.TLI)) {} + ARMTTIImpl &operator=(const ARMTTIImpl &RHS) { + BaseT::operator=(static_cast(RHS)); + ST = RHS.ST; + TLI = RHS.TLI; + return *this; + } + ARMTTIImpl &operator=(ARMTTIImpl &&RHS) { + BaseT::operator=(std::move(static_cast(RHS))); + ST = std::move(RHS.ST); + TLI = std::move(RHS.TLI); + return *this; + } + + /// \name Scalar TTI Implementations + /// @{ + + using BaseT::getIntImmCost; + unsigned getIntImmCost(const APInt &Imm, Type *Ty); + + /// @} + + /// \name Vector TTI Implementations + /// @{ + + unsigned getNumberOfRegisters(bool Vector) { + if (Vector) { + if (ST->hasNEON()) + return 16; + return 0; + } + + if (ST->isThumb1Only()) + return 8; + return 13; + } + + unsigned getRegisterBitWidth(bool Vector) { + if (Vector) { + if (ST->hasNEON()) + return 128; + return 0; + } + + return 32; + } + + unsigned getMaxInterleaveFactor() { + // These are out of order CPUs: + if (ST->isCortexA15() || ST->isSwift()) + return 2; + return 1; + } + + unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, + Type *SubTp); + + unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src); + + unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy); + + unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); + + unsigned getAddressComputationCost(Type *Val, bool IsComplex); + + unsigned getArithmeticInstrCost( + unsigned Opcode, Type *Ty, + TTI::OperandValueKind Op1Info = TTI::OK_AnyValue, + TTI::OperandValueKind Op2Info = TTI::OK_AnyValue, + TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, + TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None); + + unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, + unsigned AddressSpace); + + /// @} +}; + +} // end namespace llvm + +#endif diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index 1a5d21e6ede..54b57dd76e3 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -238,17 +238,18 @@ void MipsPassConfig::addPreRegAlloc() { addPass(createMipsOptimizePICCallPass(getMipsTargetMachine())); } -void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) { +TargetTransformInfo MipsTargetMachine::getTTI() { if (Subtarget->allowMixed16_32()) { - DEBUG(errs() << "No "); + DEBUG(errs() << "No Target Transform Info Pass Added\n"); //FIXME: The Basic Target Transform Info // pass needs to become a function pass instead of // being an immutable pass and then this method as it exists now // would be unnecessary. - PM.add(createNoTargetTransformInfoPass(getDataLayout())); - } else - LLVMTargetMachine::addAnalysisPasses(PM); + return TargetTransformInfo(getDataLayout()); + } + DEBUG(errs() << "Target Transform Info Pass Added\n"); + return LLVMTargetMachine::getTTI(); } // Implemented by targets that want to run passes immediately before diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h index d13f18588b5..e364dc2e41a 100644 --- a/lib/Target/Mips/MipsTargetMachine.h +++ b/lib/Target/Mips/MipsTargetMachine.h @@ -44,7 +44,7 @@ public: CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle); ~MipsTargetMachine() override; - void addAnalysisPasses(PassManagerBase &PM) override; + TargetTransformInfo getTTI() override; const DataLayout *getDataLayout() const override { return &DL; } const MipsSubtarget *getSubtargetImpl() const override { diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/lib/Target/NVPTX/NVPTXTargetMachine.cpp index 0b74372c852..aacf7dcdcf9 100644 --- a/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -17,6 +17,7 @@ #include "NVPTXAllocaHoisting.h" #include "NVPTXLowerAggrCopies.h" #include "NVPTXTargetObjectFile.h" +#include "NVPTXTargetTransformInfo.h" #include "llvm/Analysis/Passes.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineFunctionAnalysis.h" @@ -136,8 +137,8 @@ TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) { return PassConfig; } -void NVPTXTargetMachine::addAnalysisPasses(PassManagerBase &PM) { - PM.add(createNVPTXTargetTransformInfoPass(this)); +TargetTransformInfo NVPTXTargetMachine::getTTI() { + return TargetTransformInfo(NVPTXTTIImpl(this)); } void NVPTXPassConfig::addIRPasses() { diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.h b/lib/Target/NVPTX/NVPTXTargetMachine.h index c76ad42f78c..3b9511210c7 100644 --- a/lib/Target/NVPTX/NVPTXTargetMachine.h +++ b/lib/Target/NVPTX/NVPTXTargetMachine.h @@ -56,8 +56,7 @@ public: return TLOF.get(); } - /// \brief Register NVPTX analysis passes with a pass manager. - void addAnalysisPasses(PassManagerBase &PM) override; + TargetTransformInfo getTTI() override; }; // NVPTXTargetMachine. diff --git a/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp b/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp index c7a03c74f4a..b8af04de24a 100644 --- a/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp +++ b/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp @@ -1,4 +1,4 @@ -//===-- NVPTXTargetTransformInfo.cpp - NVPTX specific TTI pass ---------===// +//===-- NVPTXTargetTransformInfo.cpp - NVPTX specific TTI -----------------===// // // The LLVM Compiler Infrastructure // @@ -6,16 +6,8 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// -// \file -// This file implements a TargetTransformInfo analysis pass specific to the -// NVPTX target machine. It uses the target's detailed information to provide -// more precise answers to certain TTI queries, while letting the target -// independent and default TTI implementations handle the rest. -// -//===----------------------------------------------------------------------===// -#include "NVPTXTargetMachine.h" +#include "NVPTXTargetTransformInfo.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/ValueTracking.h" @@ -27,52 +19,6 @@ using namespace llvm; #define DEBUG_TYPE "NVPTXtti" -namespace { - -class NVPTXTTIImpl : public BasicTTIImplBase { - typedef BasicTTIImplBase BaseT; - typedef TargetTransformInfo TTI; - - const NVPTXTargetLowering *TLI; - -public: - explicit NVPTXTTIImpl(const NVPTXTargetMachine *TM = nullptr) - : BaseT(TM), - TLI(TM ? TM->getSubtargetImpl()->getTargetLowering() : nullptr) {} - - // Provide value semantics. MSVC requires that we spell all of these out. - NVPTXTTIImpl(const NVPTXTTIImpl &Arg) - : BaseT(static_cast(Arg)), TLI(Arg.TLI) {} - NVPTXTTIImpl(NVPTXTTIImpl &&Arg) - : BaseT(std::move(static_cast(Arg))), TLI(std::move(Arg.TLI)) {} - NVPTXTTIImpl &operator=(const NVPTXTTIImpl &RHS) { - BaseT::operator=(static_cast(RHS)); - TLI = RHS.TLI; - return *this; - } - NVPTXTTIImpl &operator=(NVPTXTTIImpl &&RHS) { - BaseT::operator=(std::move(static_cast(RHS))); - TLI = std::move(RHS.TLI); - return *this; - } - - bool hasBranchDivergence() { return true; } - - unsigned getArithmeticInstrCost( - unsigned Opcode, Type *Ty, - TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, - TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, - TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, - TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None); -}; - -} // end anonymous namespace - -ImmutablePass * -llvm::createNVPTXTargetTransformInfoPass(const NVPTXTargetMachine *TM) { - return new TargetTransformInfoWrapperPass(NVPTXTTIImpl(TM)); -} - unsigned NVPTXTTIImpl::getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, diff --git a/lib/Target/NVPTX/NVPTXTargetTransformInfo.h b/lib/Target/NVPTX/NVPTXTargetTransformInfo.h new file mode 100644 index 00000000000..990de81cb7b --- /dev/null +++ b/lib/Target/NVPTX/NVPTXTargetTransformInfo.h @@ -0,0 +1,67 @@ +//===-- NVPTXTargetTransformInfo.h - NVPTX specific TTI ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// \file +/// This file a TargetTransformInfo::Concept conforming object specific to the +/// NVPTX target machine. It uses the target's detailed information to +/// provide more precise answers to certain TTI queries, while letting the +/// target independent and default TTI implementations handle the rest. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H +#define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H + +#include "NVPTX.h" +#include "NVPTXTargetMachine.h" +#include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/BasicTTIImpl.h" +#include "llvm/Target/TargetLowering.h" + +namespace llvm { + +class NVPTXTTIImpl : public BasicTTIImplBase { + typedef BasicTTIImplBase BaseT; + typedef TargetTransformInfo TTI; + + const NVPTXTargetLowering *TLI; + +public: + explicit NVPTXTTIImpl(const NVPTXTargetMachine *TM = nullptr) + : BaseT(TM), + TLI(TM ? TM->getSubtargetImpl()->getTargetLowering() : nullptr) {} + + // Provide value semantics. MSVC requires that we spell all of these out. + NVPTXTTIImpl(const NVPTXTTIImpl &Arg) + : BaseT(static_cast(Arg)), TLI(Arg.TLI) {} + NVPTXTTIImpl(NVPTXTTIImpl &&Arg) + : BaseT(std::move(static_cast(Arg))), TLI(std::move(Arg.TLI)) {} + NVPTXTTIImpl &operator=(const NVPTXTTIImpl &RHS) { + BaseT::operator=(static_cast(RHS)); + TLI = RHS.TLI; + return *this; + } + NVPTXTTIImpl &operator=(NVPTXTTIImpl &&RHS) { + BaseT::operator=(std::move(static_cast(RHS))); + TLI = std::move(RHS.TLI); + return *this; + } + + bool hasBranchDivergence() { return true; } + + unsigned getArithmeticInstrCost( + unsigned Opcode, Type *Ty, + TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, + TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, + TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, + TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None); +}; + +} // end namespace llvm + +#endif diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index 8121d7f7857..ba061cfd6ef 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -14,6 +14,7 @@ #include "PPCTargetMachine.h" #include "PPC.h" #include "PPCTargetObjectFile.h" +#include "PPCTargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/IR/Function.h" #include "llvm/MC/MCStreamer.h" @@ -274,6 +275,6 @@ void PPCPassConfig::addPreEmitPass() { addPass(createPPCBranchSelectionPass(), false); } -void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) { - PM.add(createPPCTargetTransformInfoPass(this)); +TargetTransformInfo PPCTargetMachine::getTTI() { + return TargetTransformInfo(PPCTTIImpl(this)); } diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h index e3958412f15..7786a14f3a9 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.h +++ b/lib/Target/PowerPC/PPCTargetMachine.h @@ -45,8 +45,8 @@ public: // Pass Pipeline Configuration TargetPassConfig *createPassConfig(PassManagerBase &PM) override; - /// \brief Register PPC analysis passes with a pass manager. - void addAnalysisPasses(PassManagerBase &PM) override; + TargetTransformInfo getTTI() override; + TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } diff --git a/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 6bdee25477c..3519229eb09 100644 --- a/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -1,4 +1,4 @@ -//===-- PPCTargetTransformInfo.cpp - PPC specific TTI pass ----------------===// +//===-- PPCTargetTransformInfo.cpp - PPC specific TTI ---------------------===// // // The LLVM Compiler Infrastructure // @@ -6,16 +6,8 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -/// \file -/// This file implements a TargetTransformInfo analysis pass specific to the -/// PPC target machine. It uses the target's detailed information to provide -/// more precise answers to certain TTI queries, while letting the target -/// independent and default TTI implementations handle the rest. -/// -//===----------------------------------------------------------------------===// -#include "PPC.h" -#include "PPCTargetMachine.h" +#include "PPCTargetTransformInfo.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/BasicTTIImpl.h" #include "llvm/Support/CommandLine.h" @@ -29,86 +21,6 @@ using namespace llvm; static cl::opt DisablePPCConstHoist("disable-ppc-constant-hoisting", cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden); -namespace { - -class PPCTTIImpl : public BasicTTIImplBase { - typedef BasicTTIImplBase BaseT; - typedef TargetTransformInfo TTI; - - const PPCSubtarget *ST; - const PPCTargetLowering *TLI; - -public: - explicit PPCTTIImpl(const PPCTargetMachine *TM = nullptr) - : BaseT(TM), ST(TM->getSubtargetImpl()), TLI(ST->getTargetLowering()) {} - - // Provide value semantics. MSVC requires that we spell all of these out. - PPCTTIImpl(const PPCTTIImpl &Arg) - : BaseT(static_cast(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} - PPCTTIImpl(PPCTTIImpl &&Arg) - : BaseT(std::move(static_cast(Arg))), ST(std::move(Arg.ST)), - TLI(std::move(Arg.TLI)) {} - PPCTTIImpl &operator=(const PPCTTIImpl &RHS) { - BaseT::operator=(static_cast(RHS)); - ST = RHS.ST; - TLI = RHS.TLI; - return *this; - } - PPCTTIImpl &operator=(PPCTTIImpl &&RHS) { - BaseT::operator=(std::move(static_cast(RHS))); - ST = std::move(RHS.ST); - TLI = std::move(RHS.TLI); - return *this; - } - - /// \name Scalar TTI Implementations - /// @{ - - using BaseT::getIntImmCost; - unsigned getIntImmCost(const APInt &Imm, Type *Ty); - - unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, - Type *Ty); - unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, - Type *Ty); - - TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth); - void getUnrollingPreferences(const Function *F, Loop *L, - TTI::UnrollingPreferences &UP); - - /// @} - - /// \name Vector TTI Implementations - /// @{ - - unsigned getNumberOfRegisters(bool Vector); - unsigned getRegisterBitWidth(bool Vector); - unsigned getMaxInterleaveFactor(); - unsigned getArithmeticInstrCost( - unsigned Opcode, Type *Ty, - TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, - TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, - TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, - TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None); - unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, - Type *SubTp); - unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src); - unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy); - unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); - unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, - unsigned AddressSpace); - - /// @} -}; - -} // end anonymous namespace - -ImmutablePass * -llvm::createPPCTargetTransformInfoPass(const PPCTargetMachine *TM) { - return new TargetTransformInfoWrapperPass(PPCTTIImpl(TM)); -} - - //===----------------------------------------------------------------------===// // // PPC cost model. diff --git a/lib/Target/PowerPC/PPCTargetTransformInfo.h b/lib/Target/PowerPC/PPCTargetTransformInfo.h new file mode 100644 index 00000000000..10d587ec376 --- /dev/null +++ b/lib/Target/PowerPC/PPCTargetTransformInfo.h @@ -0,0 +1,100 @@ +//===-- PPCTargetTransformInfo.h - PPC specific TTI -------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// \file +/// This file a TargetTransformInfo::Concept conforming object specific to the +/// PPC target machine. It uses the target's detailed information to +/// provide more precise answers to certain TTI queries, while letting the +/// target independent and default TTI implementations handle the rest. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H +#define LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H + +#include "PPC.h" +#include "PPCTargetMachine.h" +#include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/BasicTTIImpl.h" +#include "llvm/Target/TargetLowering.h" + +namespace llvm { + +class PPCTTIImpl : public BasicTTIImplBase { + typedef BasicTTIImplBase BaseT; + typedef TargetTransformInfo TTI; + + const PPCSubtarget *ST; + const PPCTargetLowering *TLI; + +public: + explicit PPCTTIImpl(const PPCTargetMachine *TM = nullptr) + : BaseT(TM), ST(TM->getSubtargetImpl()), TLI(ST->getTargetLowering()) {} + + // Provide value semantics. MSVC requires that we spell all of these out. + PPCTTIImpl(const PPCTTIImpl &Arg) + : BaseT(static_cast(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} + PPCTTIImpl(PPCTTIImpl &&Arg) + : BaseT(std::move(static_cast(Arg))), ST(std::move(Arg.ST)), + TLI(std::move(Arg.TLI)) {} + PPCTTIImpl &operator=(const PPCTTIImpl &RHS) { + BaseT::operator=(static_cast(RHS)); + ST = RHS.ST; + TLI = RHS.TLI; + return *this; + } + PPCTTIImpl &operator=(PPCTTIImpl &&RHS) { + BaseT::operator=(std::move(static_cast(RHS))); + ST = std::move(RHS.ST); + TLI = std::move(RHS.TLI); + return *this; + } + + /// \name Scalar TTI Implementations + /// @{ + + using BaseT::getIntImmCost; + unsigned getIntImmCost(const APInt &Imm, Type *Ty); + + unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, + Type *Ty); + unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, + Type *Ty); + + TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth); + void getUnrollingPreferences(const Function *F, Loop *L, + TTI::UnrollingPreferences &UP); + + /// @} + + /// \name Vector TTI Implementations + /// @{ + + unsigned getNumberOfRegisters(bool Vector); + unsigned getRegisterBitWidth(bool Vector); + unsigned getMaxInterleaveFactor(); + unsigned getArithmeticInstrCost( + unsigned Opcode, Type *Ty, + TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, + TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, + TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, + TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None); + unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, + Type *SubTp); + unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src); + unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy); + unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); + unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, + unsigned AddressSpace); + + /// @} +}; + +} // end namespace llvm + +#endif diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp b/lib/Target/R600/AMDGPUTargetMachine.cpp index 5c4ef1cd22a..b43a63e5805 100644 --- a/lib/Target/R600/AMDGPUTargetMachine.cpp +++ b/lib/Target/R600/AMDGPUTargetMachine.cpp @@ -15,6 +15,7 @@ #include "AMDGPUTargetMachine.h" #include "AMDGPU.h" +#include "AMDGPUTargetTransformInfo.h" #include "R600ISelLowering.h" #include "R600InstrInfo.h" #include "R600MachineScheduler.h" @@ -116,11 +117,11 @@ TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) { } //===----------------------------------------------------------------------===// -// AMDGPU Analysis Pass Setup +// AMDGPU Pass Setup //===----------------------------------------------------------------------===// -void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) { - PM.add(createAMDGPUTargetTransformInfoPass(this)); +TargetTransformInfo AMDGPUTargetMachine::getTTI() { + return TargetTransformInfo(AMDGPUTTIImpl(this)); } void AMDGPUPassConfig::addIRPasses() { diff --git a/lib/Target/R600/AMDGPUTargetMachine.h b/lib/Target/R600/AMDGPUTargetMachine.h index 8aa97cfd987..17cb28cd63e 100644 --- a/lib/Target/R600/AMDGPUTargetMachine.h +++ b/lib/Target/R600/AMDGPUTargetMachine.h @@ -55,8 +55,8 @@ public: } TargetPassConfig *createPassConfig(PassManagerBase &PM) override; - /// \brief Register R600 analysis passes with a pass manager. - void addAnalysisPasses(PassManagerBase &PM) override; + TargetTransformInfo getTTI() override; + TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF; } diff --git a/lib/Target/R600/AMDGPUTargetTransformInfo.cpp b/lib/Target/R600/AMDGPUTargetTransformInfo.cpp index 132765ab9b0..be7b2f42971 100644 --- a/lib/Target/R600/AMDGPUTargetTransformInfo.cpp +++ b/lib/Target/R600/AMDGPUTargetTransformInfo.cpp @@ -15,8 +15,7 @@ // //===----------------------------------------------------------------------===// -#include "AMDGPU.h" -#include "AMDGPUTargetMachine.h" +#include "AMDGPUTargetTransformInfo.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/ValueTracking.h" @@ -28,56 +27,6 @@ using namespace llvm; #define DEBUG_TYPE "AMDGPUtti" -namespace { - -class AMDGPUTTIImpl : public BasicTTIImplBase { - typedef BasicTTIImplBase BaseT; - typedef TargetTransformInfo TTI; - - const AMDGPUSubtarget *ST; - -public: - explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM = nullptr) - : BaseT(TM), ST(TM->getSubtargetImpl()) {} - - // Provide value semantics. MSVC requires that we spell all of these out. - AMDGPUTTIImpl(const AMDGPUTTIImpl &Arg) - : BaseT(static_cast(Arg)), ST(Arg.ST) {} - AMDGPUTTIImpl(AMDGPUTTIImpl &&Arg) - : BaseT(std::move(static_cast(Arg))), ST(std::move(Arg.ST)) {} - AMDGPUTTIImpl &operator=(const AMDGPUTTIImpl &RHS) { - BaseT::operator=(static_cast(RHS)); - ST = RHS.ST; - return *this; - } - AMDGPUTTIImpl &operator=(AMDGPUTTIImpl &&RHS) { - BaseT::operator=(std::move(static_cast(RHS))); - ST = std::move(RHS.ST); - return *this; - } - - bool hasBranchDivergence() { return true; } - - void getUnrollingPreferences(const Function *F, Loop *L, - TTI::UnrollingPreferences &UP); - - TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) { - assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); - return ST->hasBCNT(TyWidth) ? TTI::PSK_FastHardware : TTI::PSK_Software; - } - - unsigned getNumberOfRegisters(bool Vector); - unsigned getRegisterBitWidth(bool Vector); - unsigned getMaxInterleaveFactor(); -}; - -} // end anonymous namespace - -ImmutablePass * -llvm::createAMDGPUTargetTransformInfoPass(const AMDGPUTargetMachine *TM) { - return new TargetTransformInfoWrapperPass(AMDGPUTTIImpl(TM)); -} - void AMDGPUTTIImpl::getUnrollingPreferences(const Function *, Loop *L, TTI::UnrollingPreferences &UP) { UP.Threshold = 300; // Twice the default. diff --git a/lib/Target/R600/AMDGPUTargetTransformInfo.h b/lib/Target/R600/AMDGPUTargetTransformInfo.h new file mode 100644 index 00000000000..abf692bec82 --- /dev/null +++ b/lib/Target/R600/AMDGPUTargetTransformInfo.h @@ -0,0 +1,71 @@ +//===-- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// \file +/// This file a TargetTransformInfo::Concept conforming object specific to the +/// AMDGPU target machine. It uses the target's detailed information to +/// provide more precise answers to certain TTI queries, while letting the +/// target independent and default TTI implementations handle the rest. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_R600_AMDGPUTARGETTRANSFORMINFO_H +#define LLVM_LIB_TARGET_R600_AMDGPUTARGETTRANSFORMINFO_H + +#include "AMDGPU.h" +#include "AMDGPUTargetMachine.h" +#include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/BasicTTIImpl.h" +#include "llvm/Target/TargetLowering.h" + +namespace llvm { + +class AMDGPUTTIImpl : public BasicTTIImplBase { + typedef BasicTTIImplBase BaseT; + typedef TargetTransformInfo TTI; + + const AMDGPUSubtarget *ST; + +public: + explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM = nullptr) + : BaseT(TM), ST(TM->getSubtargetImpl()) {} + + // Provide value semantics. MSVC requires that we spell all of these out. + AMDGPUTTIImpl(const AMDGPUTTIImpl &Arg) + : BaseT(static_cast(Arg)), ST(Arg.ST) {} + AMDGPUTTIImpl(AMDGPUTTIImpl &&Arg) + : BaseT(std::move(static_cast(Arg))), ST(std::move(Arg.ST)) {} + AMDGPUTTIImpl &operator=(const AMDGPUTTIImpl &RHS) { + BaseT::operator=(static_cast(RHS)); + ST = RHS.ST; + return *this; + } + AMDGPUTTIImpl &operator=(AMDGPUTTIImpl &&RHS) { + BaseT::operator=(std::move(static_cast(RHS))); + ST = std::move(RHS.ST); + return *this; + } + + bool hasBranchDivergence() { return true; } + + void getUnrollingPreferences(const Function *F, Loop *L, + TTI::UnrollingPreferences &UP); + + TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) { + assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); + return ST->hasBCNT(TyWidth) ? TTI::PSK_FastHardware : TTI::PSK_Software; + } + + unsigned getNumberOfRegisters(bool Vector); + unsigned getRegisterBitWidth(bool Vector); + unsigned getMaxInterleaveFactor(); +}; + +} // end namespace llvm + +#endif diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp index 2b683adfa9c..a8c877f848a 100644 --- a/lib/Target/TargetMachine.cpp +++ b/lib/Target/TargetMachine.cpp @@ -172,8 +172,8 @@ void TargetMachine::setDataSections(bool V) { Options.DataSections = V; } -void TargetMachine::addAnalysisPasses(PassManagerBase &PM) { - PM.add(createNoTargetTransformInfoPass(getDataLayout())); +TargetTransformInfo TargetMachine::getTTI() { + return TargetTransformInfo(getDataLayout()); } static bool canUsePrivateLabel(const MCAsmInfo &AsmInfo, diff --git a/lib/Target/TargetMachineC.cpp b/lib/Target/TargetMachineC.cpp index 0a80b4addb3..9d759a3e644 100644 --- a/lib/Target/TargetMachineC.cpp +++ b/lib/Target/TargetMachineC.cpp @@ -14,6 +14,7 @@ #include "llvm-c/TargetMachine.h" #include "llvm-c/Core.h" #include "llvm-c/Target.h" +#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/Module.h" #include "llvm/PassManager.h" @@ -255,5 +256,5 @@ char *LLVMGetDefaultTargetTriple(void) { } void LLVMAddAnalysisPasses(LLVMTargetMachineRef T, LLVMPassManagerRef PM) { - unwrap(T)->addAnalysisPasses(*unwrap(PM)); + unwrap(PM)->add(createTargetTransformInfoWrapperPass(unwrap(T)->getTTI())); } diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index 5988b9aad70..ea37b29cc5e 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -14,6 +14,7 @@ #include "X86TargetMachine.h" #include "X86.h" #include "X86TargetObjectFile.h" +#include "X86TargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/IR/Function.h" #include "llvm/PassManager.h" @@ -161,11 +162,11 @@ UseVZeroUpper("x86-use-vzeroupper", cl::Hidden, cl::init(true)); //===----------------------------------------------------------------------===// -// X86 Analysis Pass Setup +// X86 TTI query. //===----------------------------------------------------------------------===// -void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) { - PM.add(createX86TargetTransformInfoPass(this)); +TargetTransformInfo X86TargetMachine::getTTI() { + return TargetTransformInfo(X86TTIImpl(this)); } diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index bcf40e835a1..83f71a7bcc2 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -39,8 +39,7 @@ public: const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; } const X86Subtarget *getSubtargetImpl(const Function &F) const override; - /// \brief Register X86 analysis passes with a pass manager. - void addAnalysisPasses(PassManagerBase &PM) override; + TargetTransformInfo getTTI() override; // Set up the pass pipeline. TargetPassConfig *createPassConfig(PassManagerBase &PM) override; diff --git a/lib/Target/X86/X86TargetTransformInfo.cpp b/lib/Target/X86/X86TargetTransformInfo.cpp index d792f930fc4..5136619235b 100644 --- a/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/lib/Target/X86/X86TargetTransformInfo.cpp @@ -14,8 +14,7 @@ /// //===----------------------------------------------------------------------===// -#include "X86.h" -#include "X86TargetMachine.h" +#include "X86TargetTransformInfo.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/BasicTTIImpl.h" #include "llvm/IR/IntrinsicInst.h" @@ -26,95 +25,6 @@ using namespace llvm; #define DEBUG_TYPE "x86tti" -namespace { - -class X86TTIImpl : public BasicTTIImplBase { - typedef BasicTTIImplBase BaseT; - typedef TargetTransformInfo TTI; - - const X86Subtarget *ST; - const X86TargetLowering *TLI; - - unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract); - -public: - explicit X86TTIImpl(const X86TargetMachine *TM = nullptr) - : BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr), - TLI(ST ? ST->getTargetLowering() : nullptr) {} - - // Provide value semantics. MSVC requires that we spell all of these out. - X86TTIImpl(const X86TTIImpl &Arg) - : BaseT(static_cast(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} - X86TTIImpl(X86TTIImpl &&Arg) - : BaseT(std::move(static_cast(Arg))), ST(std::move(Arg.ST)), - TLI(std::move(Arg.TLI)) {} - X86TTIImpl &operator=(const X86TTIImpl &RHS) { - BaseT::operator=(static_cast(RHS)); - ST = RHS.ST; - TLI = RHS.TLI; - return *this; - } - X86TTIImpl &operator=(X86TTIImpl &&RHS) { - BaseT::operator=(std::move(static_cast(RHS))); - ST = std::move(RHS.ST); - TLI = std::move(RHS.TLI); - return *this; - } - - /// \name Scalar TTI Implementations - /// @{ - TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth); - - /// @} - - /// \name Vector TTI Implementations - /// @{ - - unsigned getNumberOfRegisters(bool Vector); - unsigned getRegisterBitWidth(bool Vector); - unsigned getMaxInterleaveFactor(); - unsigned getArithmeticInstrCost( - unsigned Opcode, Type *Ty, - TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, - TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, - TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, - TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None); - unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, - Type *SubTp); - unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src); - unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy); - unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); - unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, - unsigned AddressSpace); - unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, - unsigned AddressSpace); - - unsigned getAddressComputationCost(Type *PtrTy, bool IsComplex); - - unsigned getReductionCost(unsigned Opcode, Type *Ty, bool IsPairwiseForm); - - unsigned getIntImmCost(int64_t); - - unsigned getIntImmCost(const APInt &Imm, Type *Ty); - - unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, - Type *Ty); - unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, - Type *Ty); - bool isLegalMaskedLoad(Type *DataType, int Consecutive); - bool isLegalMaskedStore(Type *DataType, int Consecutive); - - /// @} -}; - -} // end anonymous namespace - -ImmutablePass * -llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) { - return new TargetTransformInfoWrapperPass(X86TTIImpl(TM)); -} - - //===----------------------------------------------------------------------===// // // X86 cost model. diff --git a/lib/Target/X86/X86TargetTransformInfo.h b/lib/Target/X86/X86TargetTransformInfo.h new file mode 100644 index 00000000000..26b8e53880f --- /dev/null +++ b/lib/Target/X86/X86TargetTransformInfo.h @@ -0,0 +1,110 @@ +//===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// \file +/// This file a TargetTransformInfo::Concept conforming object specific to the +/// X86 target machine. It uses the target's detailed information to +/// provide more precise answers to certain TTI queries, while letting the +/// target independent and default TTI implementations handle the rest. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H +#define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H + +#include "X86.h" +#include "X86TargetMachine.h" +#include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/BasicTTIImpl.h" +#include "llvm/Target/TargetLowering.h" + +namespace llvm { + +class X86TTIImpl : public BasicTTIImplBase { + typedef BasicTTIImplBase BaseT; + typedef TargetTransformInfo TTI; + + const X86Subtarget *ST; + const X86TargetLowering *TLI; + + unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract); + +public: + explicit X86TTIImpl(const X86TargetMachine *TM = nullptr) + : BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr), + TLI(ST ? ST->getTargetLowering() : nullptr) {} + + // Provide value semantics. MSVC requires that we spell all of these out. + X86TTIImpl(const X86TTIImpl &Arg) + : BaseT(static_cast(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} + X86TTIImpl(X86TTIImpl &&Arg) + : BaseT(std::move(static_cast(Arg))), ST(std::move(Arg.ST)), + TLI(std::move(Arg.TLI)) {} + X86TTIImpl &operator=(const X86TTIImpl &RHS) { + BaseT::operator=(static_cast(RHS)); + ST = RHS.ST; + TLI = RHS.TLI; + return *this; + } + X86TTIImpl &operator=(X86TTIImpl &&RHS) { + BaseT::operator=(std::move(static_cast(RHS))); + ST = std::move(RHS.ST); + TLI = std::move(RHS.TLI); + return *this; + } + + /// \name Scalar TTI Implementations + /// @{ + TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth); + + /// @} + + /// \name Vector TTI Implementations + /// @{ + + unsigned getNumberOfRegisters(bool Vector); + unsigned getRegisterBitWidth(bool Vector); + unsigned getMaxInterleaveFactor(); + unsigned getArithmeticInstrCost( + unsigned Opcode, Type *Ty, + TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, + TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, + TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, + TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None); + unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, + Type *SubTp); + unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src); + unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy); + unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); + unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, + unsigned AddressSpace); + unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, + unsigned AddressSpace); + + unsigned getAddressComputationCost(Type *PtrTy, bool IsComplex); + + unsigned getReductionCost(unsigned Opcode, Type *Ty, bool IsPairwiseForm); + + unsigned getIntImmCost(int64_t); + + unsigned getIntImmCost(const APInt &Imm, Type *Ty); + + unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, + Type *Ty); + unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, + Type *Ty); + bool isLegalMaskedLoad(Type *DataType, int Consecutive); + bool isLegalMaskedStore(Type *DataType, int Consecutive); + + /// @} +}; +; + +} // end namespace llvm + +#endif diff --git a/lib/Target/XCore/CMakeLists.txt b/lib/Target/XCore/CMakeLists.txt index 5ad07544ef8..0a609ef76f4 100644 --- a/lib/Target/XCore/CMakeLists.txt +++ b/lib/Target/XCore/CMakeLists.txt @@ -22,7 +22,6 @@ add_llvm_target(XCoreCodeGen XCoreSubtarget.cpp XCoreTargetMachine.cpp XCoreTargetObjectFile.cpp - XCoreTargetTransformInfo.cpp XCoreSelectionDAGInfo.cpp XCoreFrameToArgsOffsetElim.cpp ) diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp index 82df1c984be..d6832a372d1 100644 --- a/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/lib/Target/XCore/XCoreTargetMachine.cpp @@ -12,6 +12,7 @@ #include "XCoreTargetMachine.h" #include "XCoreTargetObjectFile.h" +#include "XCoreTargetTransformInfo.h" #include "XCore.h" #include "llvm/CodeGen/Passes.h" #include "llvm/IR/Module.h" @@ -82,6 +83,6 @@ extern "C" void LLVMInitializeXCoreTarget() { RegisterTargetMachine X(TheXCoreTarget); } -void XCoreTargetMachine::addAnalysisPasses(PassManagerBase &PM) { - PM.add(createXCoreTargetTransformInfoPass(this)); +TargetTransformInfo XCoreTargetMachine::getTTI() { + return TargetTransformInfo(XCoreTTIImpl(this)); } diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h index c18de6caf4a..ea9c36b02d5 100644 --- a/lib/Target/XCore/XCoreTargetMachine.h +++ b/lib/Target/XCore/XCoreTargetMachine.h @@ -36,7 +36,7 @@ public: // Pass Pipeline Configuration TargetPassConfig *createPassConfig(PassManagerBase &PM) override; - void addAnalysisPasses(PassManagerBase &PM) override; + TargetTransformInfo getTTI() override; TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } diff --git a/lib/Target/XCore/XCoreTargetTransformInfo.cpp b/lib/Target/XCore/XCoreTargetTransformInfo.h similarity index 69% rename from lib/Target/XCore/XCoreTargetTransformInfo.cpp rename to lib/Target/XCore/XCoreTargetTransformInfo.h index d2b152fc82e..5c2f36ff395 100644 --- a/lib/Target/XCore/XCoreTargetTransformInfo.cpp +++ b/lib/Target/XCore/XCoreTargetTransformInfo.h @@ -1,4 +1,4 @@ -//===-- XCoreTargetTransformInfo.cpp - XCore specific TTI pass ----------------===// +//===-- XCoreTargetTransformInfo.h - XCore specific TTI ---------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,25 +7,23 @@ // //===----------------------------------------------------------------------===// /// \file -/// This file implements a TargetTransformInfo analysis pass specific to the -/// XCore target machine. It uses the target's detailed information to provide -/// more precise answers to certain TTI queries, while letting the target -/// independent and default TTI implementations handle the rest. +/// This file a TargetTransformInfo::Concept conforming object specific to the +/// XCore target machine. It uses the target's detailed information to +/// provide more precise answers to certain TTI queries, while letting the +/// target independent and default TTI implementations handle the rest. /// //===----------------------------------------------------------------------===// +#ifndef LLVM_LIB_TARGET_XCORE_XCORETARGETTRANSFORMINFO_H +#define LLVM_LIB_TARGET_XCORE_XCORETARGETTRANSFORMINFO_H + #include "XCore.h" #include "XCoreTargetMachine.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/BasicTTIImpl.h" -#include "llvm/Support/Debug.h" -#include "llvm/Target/CostTable.h" #include "llvm/Target/TargetLowering.h" -using namespace llvm; - -#define DEBUG_TYPE "xcoretti" -namespace { +namespace llvm { class XCoreTTIImpl : public BasicTTIImplBase { typedef BasicTTIImplBase BaseT; @@ -50,15 +48,12 @@ public: unsigned getNumberOfRegisters(bool Vector) { if (Vector) { - return 0; + return 0; } return 12; } }; -} // end anonymous namespace +} // end namespace llvm -ImmutablePass * -llvm::createXCoreTargetTransformInfoPass(const XCoreTargetMachine *TM) { - return new TargetTransformInfoWrapperPass(XCoreTTIImpl(TM)); -} +#endif diff --git a/tools/opt/opt.cpp b/tools/opt/opt.cpp index 4f4f858142c..93b44d4f7f4 100644 --- a/tools/opt/opt.cpp +++ b/tools/opt/opt.cpp @@ -427,21 +427,16 @@ int main(int argc, char **argv) { std::unique_ptr TM(Machine); // Add internal analysis passes from the target machine. - if (TM) - TM->addAnalysisPasses(Passes); - else - Passes.add(createNoTargetTransformInfoPass(DL)); + Passes.add(createTargetTransformInfoWrapperPass( + TM ? TM->getTTI() : TargetTransformInfo(DL))); std::unique_ptr FPasses; if (OptLevelO1 || OptLevelO2 || OptLevelOs || OptLevelOz || OptLevelO3) { FPasses.reset(new FunctionPassManager(M.get())); if (DL) FPasses->add(new DataLayoutPass()); - if (TM) - TM->addAnalysisPasses(*FPasses); - else - FPasses->add(createNoTargetTransformInfoPass(DL)); - + FPasses->add(createTargetTransformInfoWrapperPass( + TM ? TM->getTTI() : TargetTransformInfo(DL))); } if (PrintBreakpoints) { -- 2.34.1