From 199a1320b792c866ee6546dcbd157bebf54edaca Mon Sep 17 00:00:00 2001 From: Asaf Badouh Date: Mon, 28 Dec 2015 08:26:26 +0000 Subject: [PATCH] [X86][AVX512] Lower broadcast sub vector to vector inrtrinsics lower broadcastx to shuffles. there are two cases: 1.src is 128 bits and dest is 512 bits: in this case we will lower it to shuffle with imm = 0. 2.src is 256 bit and dest is 512 bits: in this case we will lower it to shuffle with imm = 01000100b (0x44) that way we will broadcast the 256bit source: ymm[0,1,2,3] => zmm[0,1,2,3,0,1,2,3] then it will mask it with the passthru value (in case it's mask op). Differential Revision: http://reviews.llvm.org/D15790 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256490 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IR/IntrinsicsX86.td | 60 ++++++++++++++++++ lib/Target/X86/X86ISelLowering.cpp | 17 +++++ lib/Target/X86/X86IntrinsicsInfo.h | 26 +++++++- test/CodeGen/X86/avx512-intrinsics.ll | 76 +++++++++++++++++++++++ test/CodeGen/X86/avx512dq-intrinsics.ll | 76 +++++++++++++++++++++++ test/CodeGen/X86/avx512dqvl-intrinsics.ll | 37 +++++++++++ test/CodeGen/X86/avx512vl-intrinsics.ll | 38 ++++++++++++ 7 files changed, 329 insertions(+), 1 deletion(-) diff --git a/include/llvm/IR/IntrinsicsX86.td b/include/llvm/IR/IntrinsicsX86.td index 1cf26107374..4c3703fdfa0 100644 --- a/include/llvm/IR/IntrinsicsX86.td +++ b/include/llvm/IR/IntrinsicsX86.td @@ -5050,6 +5050,66 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". Intrinsic<[llvm_v16i32_ty], [llvm_v4i32_ty, llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>; + def int_x86_avx512_mask_broadcastf32x4_256 : + GCCBuiltin<"__builtin_ia32_broadcastf32x4_256_mask">, + Intrinsic<[llvm_v8f32_ty], + [llvm_v4f32_ty, llvm_v8f32_ty, llvm_i8_ty], [IntrNoMem]>; + + def int_x86_avx512_mask_broadcastf32x4_512 : + GCCBuiltin<"__builtin_ia32_broadcastf32x4_512">, + Intrinsic<[llvm_v16f32_ty], + [llvm_v4f32_ty, llvm_v16f32_ty, llvm_i16_ty], [IntrNoMem]>; + + def int_x86_avx512_mask_broadcastf32x8_512 : + GCCBuiltin<"__builtin_ia32_broadcastf32x8_512_mask">, + Intrinsic<[llvm_v16f32_ty], + [llvm_v8f32_ty, llvm_v16f32_ty, llvm_i16_ty], [IntrNoMem]>; + + def int_x86_avx512_mask_broadcastf64x2_256 : + GCCBuiltin<"__builtin_ia32_broadcastf64x2_256_mask">, + Intrinsic<[llvm_v4f64_ty], + [llvm_v2f64_ty, llvm_v4f64_ty, llvm_i8_ty], [IntrNoMem]>; + + def int_x86_avx512_mask_broadcastf64x2_512 : + GCCBuiltin<"__builtin_ia32_broadcastf64x2_512_mask">, + Intrinsic<[llvm_v8f64_ty], + [llvm_v2f64_ty, llvm_v8f64_ty, llvm_i8_ty], [IntrNoMem]>; + + def int_x86_avx512_mask_broadcastf64x4_512 : + GCCBuiltin<"__builtin_ia32_broadcastf64x4_512">, + Intrinsic<[llvm_v8f64_ty], + [llvm_v4f64_ty, llvm_v8f64_ty, llvm_i8_ty], [IntrNoMem]>; + + def int_x86_avx512_mask_broadcasti32x4_256 : + GCCBuiltin<"__builtin_ia32_broadcasti32x4_256_mask">, + Intrinsic<[llvm_v8i32_ty], + [llvm_v4i32_ty, llvm_v8i32_ty, llvm_i8_ty], [IntrNoMem]>; + + def int_x86_avx512_mask_broadcasti32x4_512 : + GCCBuiltin<"__builtin_ia32_broadcasti32x4_512">, + Intrinsic<[llvm_v16i32_ty], + [llvm_v4i32_ty, llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>; + + def int_x86_avx512_mask_broadcasti32x8_512 : + GCCBuiltin<"__builtin_ia32_broadcasti32x8_512_mask">, + Intrinsic<[llvm_v16i32_ty], + [llvm_v8i32_ty, llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>; + + def int_x86_avx512_mask_broadcasti64x2_256 : + GCCBuiltin<"__builtin_ia32_broadcasti64x2_256_mask">, + Intrinsic<[llvm_v4i64_ty], + [llvm_v2i64_ty, llvm_v4i64_ty, llvm_i8_ty], [IntrNoMem]>; + + def int_x86_avx512_mask_broadcasti64x2_512 : + GCCBuiltin<"__builtin_ia32_broadcasti64x2_512_mask">, + Intrinsic<[llvm_v8i64_ty], + [llvm_v2i64_ty, llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>; + + def int_x86_avx512_mask_broadcasti64x4_512 : + GCCBuiltin<"__builtin_ia32_broadcasti64x4_512">, + Intrinsic<[llvm_v8i64_ty], + [llvm_v4i64_ty, llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>; + def int_x86_avx512_pbroadcastd_i32_512 : Intrinsic<[llvm_v16i32_ty], [llvm_i32_ty], [IntrNoMem]>; diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index f8a390cf8f7..182a8cd3e8a 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -16889,6 +16889,23 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl); return DAG.getNode(IntrData->Opc0, dl, VT, VMask); } + case BRCST_SUBVEC_TO_VEC: { + SDValue Src = Op.getOperand(1); + SDValue Passthru = Op.getOperand(2); + SDValue Mask = Op.getOperand(3); + EVT resVT = Passthru.getValueType(); + SDValue subVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, resVT, + DAG.getUNDEF(resVT), Src, + DAG.getIntPtrConstant(0, dl)); + SDValue immVal; + if (Src.getSimpleValueType().is256BitVector() && resVT.is512BitVector()) + immVal = DAG.getConstant(0x44, dl, MVT::i8); + else + immVal = DAG.getConstant(0, dl, MVT::i8); + return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, + subVec, subVec, immVal), + Mask, Passthru, Subtarget, DAG); + } default: break; } diff --git a/lib/Target/X86/X86IntrinsicsInfo.h b/lib/Target/X86/X86IntrinsicsInfo.h index 8acd0c5df86..cb15cc1f3c0 100644 --- a/lib/Target/X86/X86IntrinsicsInfo.h +++ b/lib/Target/X86/X86IntrinsicsInfo.h @@ -27,7 +27,7 @@ enum IntrinsicType { FMA_OP_MASK, FMA_OP_MASKZ, FMA_OP_MASK3, VPERM_3OP_MASK, VPERM_3OP_MASKZ, INTR_TYPE_SCALAR_MASK, INTR_TYPE_SCALAR_MASK_RM, INTR_TYPE_3OP_SCALAR_MASK_RM, - COMPRESS_EXPAND_IN_REG, COMPRESS_TO_MEM, + COMPRESS_EXPAND_IN_REG, COMPRESS_TO_MEM, BRCST_SUBVEC_TO_VEC, TRUNCATE_TO_MEM_VI8, TRUNCATE_TO_MEM_VI16, TRUNCATE_TO_MEM_VI32, EXPAND_FROM_MEM, BLEND, INSERT_SUBVEC, TERLOG_OP_MASK, TERLOG_OP_MASKZ, BROADCASTM, KUNPCK, CONVERT_MASK_TO_VEC, CONVERT_TO_MASK @@ -469,12 +469,36 @@ static const IntrinsicData IntrinsicsWithoutChain[] = { X86ISD::SUBV_BROADCAST, 0), X86_INTRINSIC_DATA(avx512_mask_broadcastf32x2_512, INTR_TYPE_1OP_MASK, X86ISD::SUBV_BROADCAST, 0), + X86_INTRINSIC_DATA(avx512_mask_broadcastf32x4_256, BRCST_SUBVEC_TO_VEC, + X86ISD::SHUF128, 0), + X86_INTRINSIC_DATA(avx512_mask_broadcastf32x4_512, BRCST_SUBVEC_TO_VEC, + X86ISD::SHUF128, 0), + X86_INTRINSIC_DATA(avx512_mask_broadcastf32x8_512, BRCST_SUBVEC_TO_VEC, + X86ISD::SHUF128, 0), + X86_INTRINSIC_DATA(avx512_mask_broadcastf64x2_256, BRCST_SUBVEC_TO_VEC, + X86ISD::SHUF128, 0), + X86_INTRINSIC_DATA(avx512_mask_broadcastf64x2_512, BRCST_SUBVEC_TO_VEC, + X86ISD::SHUF128, 0), + X86_INTRINSIC_DATA(avx512_mask_broadcastf64x4_512, BRCST_SUBVEC_TO_VEC, + X86ISD::SHUF128, 0), X86_INTRINSIC_DATA(avx512_mask_broadcasti32x2_128, INTR_TYPE_1OP_MASK, X86ISD::SUBV_BROADCAST, 0), X86_INTRINSIC_DATA(avx512_mask_broadcasti32x2_256, INTR_TYPE_1OP_MASK, X86ISD::SUBV_BROADCAST, 0), X86_INTRINSIC_DATA(avx512_mask_broadcasti32x2_512, INTR_TYPE_1OP_MASK, X86ISD::SUBV_BROADCAST, 0), + X86_INTRINSIC_DATA(avx512_mask_broadcasti32x4_256, BRCST_SUBVEC_TO_VEC, + X86ISD::SHUF128, 0), + X86_INTRINSIC_DATA(avx512_mask_broadcasti32x4_512, BRCST_SUBVEC_TO_VEC, + X86ISD::SHUF128, 0), + X86_INTRINSIC_DATA(avx512_mask_broadcasti32x8_512, BRCST_SUBVEC_TO_VEC, + X86ISD::SHUF128, 0), + X86_INTRINSIC_DATA(avx512_mask_broadcasti64x2_256, BRCST_SUBVEC_TO_VEC, + X86ISD::SHUF128, 0), + X86_INTRINSIC_DATA(avx512_mask_broadcasti64x2_512, BRCST_SUBVEC_TO_VEC, + X86ISD::SHUF128, 0), + X86_INTRINSIC_DATA(avx512_mask_broadcasti64x4_512, BRCST_SUBVEC_TO_VEC, + X86ISD::SHUF128, 0), X86_INTRINSIC_DATA(avx512_mask_cmp_b_128, CMP_MASK_CC, X86ISD::CMPM, 0), X86_INTRINSIC_DATA(avx512_mask_cmp_b_256, CMP_MASK_CC, X86ISD::CMPM, 0), X86_INTRINSIC_DATA(avx512_mask_cmp_b_512, CMP_MASK_CC, X86ISD::CMPM, 0), diff --git a/test/CodeGen/X86/avx512-intrinsics.ll b/test/CodeGen/X86/avx512-intrinsics.ll index 0aed97d1e8f..764e1363848 100644 --- a/test/CodeGen/X86/avx512-intrinsics.ll +++ b/test/CodeGen/X86/avx512-intrinsics.ll @@ -6343,3 +6343,79 @@ define <2 x double>@test_int_x86_avx512_mask_move_sd_rrk(<2 x double> %x0, <2 x ret <2 x double> %res } +declare <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float>, <16 x float>, i16) + +define <16 x float>@test_int_x86_avx512_mask_broadcastf32x4_512(<4 x float> %x0, <16 x float> %x2, i16 %mask) { +; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x4_512: +; CHECK: kmovw %edi, %k1 +; CHECK: vshuff32x4 $0, %zmm0, %zmm0, %zmm2 {%k1} {z} +; CHECK: vshuff32x4 $0, %zmm0, %zmm0, %zmm1 {%k1} +; CHECK: vshuff32x4 $0, %zmm0, %zmm0, %zmm0 +; CHECK: vaddps %zmm1, %zmm0, %zmm0 +; CHECK: vaddps %zmm0, %zmm2, %zmm0 + + %res1 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float> %x0, <16 x float> %x2, i16 -1) + %res2 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float> %x0, <16 x float> %x2, i16 %mask) + %res3 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float> %x0, <16 x float> zeroinitializer, i16 %mask) + %res4 = fadd <16 x float> %res1, %res2 + %res5 = fadd <16 x float> %res3, %res4 + ret <16 x float> %res5 +} + +declare <8 x double> @llvm.x86.avx512.mask.broadcastf64x4.512(<4 x double>, <8 x double>, i8) + +define <8 x double>@test_int_x86_avx512_mask_broadcastf64x4_512(<4 x double> %x0, <8 x double> %x2, i8 %mask) { +; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf64x4_512: +; CHECK: kmovw %eax, %k1 +; CHECK: vshuff64x2 $68, %zmm0, %zmm0, %zmm2 {%k1} {z} +; CHECK: vshuff64x2 $68, %zmm0, %zmm0, %zmm1 {%k1} +; CHECK: vshuff64x2 $68, %zmm0, %zmm0, %zmm0 +; CHECK: vaddpd %zmm1, %zmm0, %zmm0 +; CHECK: vaddpd %zmm0, %zmm2, %zmm0 + + %res1 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x4.512(<4 x double> %x0, <8 x double> %x2, i8 -1) + %res2 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x4.512(<4 x double> %x0, <8 x double> %x2, i8 %mask) + %res3 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x4.512(<4 x double> %x0, <8 x double> zeroinitializer, i8 %mask) + %res4 = fadd <8 x double> %res1, %res2 + %res5 = fadd <8 x double> %res3, %res4 + ret <8 x double> %res5 +} + +declare <16 x i32> @llvm.x86.avx512.mask.broadcasti32x4.512(<4 x i32>, <16 x i32>, i16) + +define <16 x i32>@test_int_x86_avx512_mask_broadcasti32x4_512(<4 x i32> %x0, <16 x i32> %x2, i16 %mask) { +; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x4_512: +; CHECK: kmovw %edi, %k1 +; CHECK: vshufi32x4 $0, %zmm0, %zmm0, %zmm2 {%k1} {z} +; CHECK: vshufi32x4 $0, %zmm0, %zmm0, %zmm1 {%k1} +; CHECK: vshufi32x4 $0, %zmm0, %zmm0, %zmm0 +; CHECK: vpaddd %zmm1, %zmm0, %zmm0 +; CHECK: vpaddd %zmm0, %zmm2, %zmm0 + + %res1 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x4.512(<4 x i32> %x0, <16 x i32> %x2, i16 -1) + %res2 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x4.512(<4 x i32> %x0, <16 x i32> %x2, i16 %mask) + %res3 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x4.512(<4 x i32> %x0, <16 x i32> zeroinitializer, i16 %mask) + %res4 = add <16 x i32> %res1, %res2 + %res5 = add <16 x i32> %res3, %res4 + ret <16 x i32> %res5 +} + +declare <8 x i64> @llvm.x86.avx512.mask.broadcasti64x4.512(<4 x i64>, <8 x i64>, i8) + +define <8 x i64>@test_int_x86_avx512_mask_broadcasti64x4_512(<4 x i64> %x0, <8 x i64> %x2, i8 %mask) { +; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti64x4_512: +; CHECK: kmovw %eax, %k1 +; CHECK: vshufi64x2 $68, %zmm0, %zmm0, %zmm2 {%k1} {z} +; CHECK: vshufi64x2 $68, %zmm0, %zmm0, %zmm1 {%k1} +; CHECK: vshufi64x2 $68, %zmm0, %zmm0, %zmm0 +; CHECK: vpaddq %zmm1, %zmm0, %zmm0 +; CHECK: vpaddq %zmm0, %zmm2, %zmm0 + + %res1 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x4.512(<4 x i64> %x0, <8 x i64> %x2, i8 -1) + %res2 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x4.512(<4 x i64> %x0, <8 x i64> %x2, i8 %mask) + %res3 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x4.512(<4 x i64> %x0, <8 x i64> zeroinitializer, i8 %mask) + %res4 = add <8 x i64> %res1, %res2 + %res5 = add <8 x i64> %res3, %res4 + ret <8 x i64> %res5 +} + diff --git a/test/CodeGen/X86/avx512dq-intrinsics.ll b/test/CodeGen/X86/avx512dq-intrinsics.ll index 19cf368cc4d..a59fe393f55 100644 --- a/test/CodeGen/X86/avx512dq-intrinsics.ll +++ b/test/CodeGen/X86/avx512dq-intrinsics.ll @@ -589,3 +589,79 @@ define <8 x i64>@test_int_x86_avx512_cvtmask2q_512(i8 %x0) { %res = call <8 x i64> @llvm.x86.avx512.cvtmask2q.512(i8 %x0) ret <8 x i64> %res } + +declare <16 x float> @llvm.x86.avx512.mask.broadcastf32x8.512(<8 x float>, <16 x float>, i16) + +define <16 x float>@test_int_x86_avx512_mask_broadcastf32x8_512(<8 x float> %x0, <16 x float> %x2, i16 %mask) { +; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x8_512: +; CHECK: kmovw %edi, %k1 +; CHECK: vshuff32x4 $68, %zmm0, %zmm0, %zmm2 {%k1} {z} +; CHECK: vshuff32x4 $68, %zmm0, %zmm0, %zmm1 {%k1} +; CHECK: vshuff32x4 $68, %zmm0, %zmm0, %zmm0 +; CHECK: vaddps %zmm1, %zmm0, %zmm0 +; CHECK: vaddps %zmm0, %zmm2, %zmm0 + + %res1 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x8.512(<8 x float> %x0, <16 x float> %x2, i16 -1) + %res2 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x8.512(<8 x float> %x0, <16 x float> %x2, i16 %mask) + %res3 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x8.512(<8 x float> %x0, <16 x float> zeroinitializer, i16 %mask) + %res4 = fadd <16 x float> %res1, %res2 + %res5 = fadd <16 x float> %res3, %res4 + ret <16 x float> %res5 +} + +declare <8 x double> @llvm.x86.avx512.mask.broadcastf64x2.512(<2 x double>, <8 x double>, i8) + +define <8 x double>@test_int_x86_avx512_mask_broadcastf64x2_512(<2 x double> %x0, <8 x double> %x2, i8 %mask) { +; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf64x2_512: +; CHECK: kmovb %edi, %k1 +; CHECK: vshuff64x2 $0, %zmm0, %zmm0, %zmm2 {%k1} {z} +; CHECK: vshuff64x2 $0, %zmm0, %zmm0, %zmm1 {%k1} +; CHECK: vshuff64x2 $0, %zmm0, %zmm0, %zmm0 +; CHECK: vaddpd %zmm1, %zmm0, %zmm0 +; CHECK: vaddpd %zmm0, %zmm2, %zmm0 + + %res1 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x2.512(<2 x double> %x0, <8 x double> %x2, i8 -1) + %res2 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x2.512(<2 x double> %x0, <8 x double> %x2, i8 %mask) + %res3 = call <8 x double> @llvm.x86.avx512.mask.broadcastf64x2.512(<2 x double> %x0, <8 x double> zeroinitializer, i8 %mask) + %res4 = fadd <8 x double> %res1, %res2 + %res5 = fadd <8 x double> %res3, %res4 + ret <8 x double> %res5 +} + +declare <16 x i32> @llvm.x86.avx512.mask.broadcasti32x8.512(<8 x i32>, <16 x i32>, i16) + +define <16 x i32>@test_int_x86_avx512_mask_broadcasti32x8_512(<8 x i32> %x0, <16 x i32> %x2, i16 %mask) { +; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x8_512: +; CHECK: kmovw %edi, %k1 +; CHECK: vshufi32x4 $68, %zmm0, %zmm0, %zmm2 {%k1} {z} +; CHECK: vshufi32x4 $68, %zmm0, %zmm0, %zmm1 {%k1} +; CHECK: vshufi32x4 $68, %zmm0, %zmm0, %zmm0 +; CHECK: vpaddd %zmm1, %zmm0, %zmm0 +; CHECK: vpaddd %zmm0, %zmm2, %zmm0 + + %res1 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x8.512(<8 x i32> %x0, <16 x i32> %x2, i16 -1) + %res2 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x8.512(<8 x i32> %x0, <16 x i32> %x2, i16 %mask) + %res3 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x8.512(<8 x i32> %x0, <16 x i32> zeroinitializer, i16 %mask) + %res4 = add <16 x i32> %res1, %res2 + %res5 = add <16 x i32> %res3, %res4 + ret <16 x i32> %res5 +} + +declare <8 x i64> @llvm.x86.avx512.mask.broadcasti64x2.512(<2 x i64>, <8 x i64>, i8) + +define <8 x i64>@test_int_x86_avx512_mask_broadcasti64x2_512(<2 x i64> %x0, <8 x i64> %x2, i8 %mask) { +; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti64x2_512: +; CHECK: kmovb %edi, %k1 +; CHECK: vshufi64x2 $0, %zmm0, %zmm0, %zmm2 {%k1} {z} +; CHECK: vshufi64x2 $0, %zmm0, %zmm0, %zmm1 {%k1} +; CHECK: vshufi64x2 $0, %zmm0, %zmm0, %zmm0 +; CHECK: vpaddq %zmm1, %zmm0, %zmm0 +; CHECK: vpaddq %zmm0, %zmm2, %zmm0 + + %res1 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x2.512(<2 x i64> %x0, <8 x i64> %x2, i8 -1) + %res2 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x2.512(<2 x i64> %x0, <8 x i64> %x2, i8 %mask) + %res3 = call <8 x i64> @llvm.x86.avx512.mask.broadcasti64x2.512(<2 x i64> %x0, <8 x i64> zeroinitializer, i8 %mask) + %res4 = add <8 x i64> %res1, %res2 + %res5 = add <8 x i64> %res3, %res4 + ret <8 x i64> %res5 +} diff --git a/test/CodeGen/X86/avx512dqvl-intrinsics.ll b/test/CodeGen/X86/avx512dqvl-intrinsics.ll index a6d517c10cd..2065322009d 100644 --- a/test/CodeGen/X86/avx512dqvl-intrinsics.ll +++ b/test/CodeGen/X86/avx512dqvl-intrinsics.ll @@ -1928,3 +1928,40 @@ define <4 x i64>@test_int_x86_avx512_cvtmask2q_256(i8 %x0) { %res = call <4 x i64> @llvm.x86.avx512.cvtmask2q.256(i8 %x0) ret <4 x i64> %res } +declare <4 x double> @llvm.x86.avx512.mask.broadcastf64x2.256(<2 x double>, <4 x double>, i8) + +define <4 x double>@test_int_x86_avx512_mask_broadcastf64x2_256(<2 x double> %x0, <4 x double> %x2, i8 %mask) { +; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf64x2_256: +; CHECK: kmovb %edi, %k1 +; CHECK: vshuff64x2 $0, %ymm0, %ymm0, %ymm2 {%k1} {z} +; CHECK: vshuff64x2 $0, %ymm0, %ymm0, %ymm1 {%k1} +; CHECK: vshuff64x2 $0, %ymm0, %ymm0, %ymm0 +; CHECK: vaddpd %ymm1, %ymm0, %ymm0 +; CHECK: vaddpd %ymm0, %ymm2, %ymm0 + + %res1 = call <4 x double> @llvm.x86.avx512.mask.broadcastf64x2.256(<2 x double> %x0, <4 x double> %x2, i8 -1) + %res2 = call <4 x double> @llvm.x86.avx512.mask.broadcastf64x2.256(<2 x double> %x0, <4 x double> %x2, i8 %mask) + %res3 = call <4 x double> @llvm.x86.avx512.mask.broadcastf64x2.256(<2 x double> %x0, <4 x double> zeroinitializer, i8 %mask) + %res4 = fadd <4 x double> %res1, %res2 + %res5 = fadd <4 x double> %res3, %res4 + ret <4 x double> %res5 +} + +declare <4 x i64> @llvm.x86.avx512.mask.broadcasti64x2.256(<2 x i64>, <4 x i64>, i8) + +define <4 x i64>@test_int_x86_avx512_mask_broadcasti64x2_256(<2 x i64> %x0, <4 x i64> %x2, i8 %mask) { +; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti64x2_256: +; CHECK: kmovb %edi, %k1 +; CHECK: vshufi64x2 $0, %ymm0, %ymm0, %ymm2 {%k1} {z} +; CHECK: vshufi64x2 $0, %ymm0, %ymm0, %ymm1 {%k1} +; CHECK: vshufi64x2 $0, %ymm0, %ymm0, %ymm0 +; CHECK: vpaddq %ymm1, %ymm0, %ymm0 +; CHECK: vpaddq %ymm0, %ymm2, %ymm0 + + %res1 = call <4 x i64> @llvm.x86.avx512.mask.broadcasti64x2.256(<2 x i64> %x0, <4 x i64> %x2, i8 -1) + %res2 = call <4 x i64> @llvm.x86.avx512.mask.broadcasti64x2.256(<2 x i64> %x0, <4 x i64> %x2, i8 %mask) + %res3 = call <4 x i64> @llvm.x86.avx512.mask.broadcasti64x2.256(<2 x i64> %x0, <4 x i64> zeroinitializer, i8 %mask) + %res4 = add <4 x i64> %res1, %res2 + %res5 = add <4 x i64> %res3, %res4 + ret <4 x i64> %res5 +} diff --git a/test/CodeGen/X86/avx512vl-intrinsics.ll b/test/CodeGen/X86/avx512vl-intrinsics.ll index 3bdbf808743..d9e8728c5ca 100644 --- a/test/CodeGen/X86/avx512vl-intrinsics.ll +++ b/test/CodeGen/X86/avx512vl-intrinsics.ll @@ -5763,3 +5763,41 @@ define <4 x float> @test_x86_vbroadcast_ss_ps_128(<4 x float> %a0, <4 x float> % } declare <4 x float> @llvm.x86.avx512.mask.broadcast.ss.ps.128(<4 x float>, <4 x float>, i8) nounwind readonly + +declare <8 x float> @llvm.x86.avx512.mask.broadcastf32x4.256(<4 x float>, <8 x float>, i8) + +define <8 x float>@test_int_x86_avx512_mask_broadcastf32x4_256(<4 x float> %x0, <8 x float> %x2, i8 %mask) { +; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x4_256: +; CHECK: kmovw %eax, %k1 +; CHECK: vshuff32x4 $0, %ymm0, %ymm0, %ymm2 {%k1} {z} +; CHECK: vshuff32x4 $0, %ymm0, %ymm0, %ymm1 {%k1} +; CHECK: vshuff32x4 $0, %ymm0, %ymm0, %ymm0 +; CHECK: vaddps %ymm1, %ymm0, %ymm0 +; CHECK: vaddps %ymm0, %ymm2, %ymm0 + + %res1 = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x4.256(<4 x float> %x0, <8 x float> %x2, i8 -1) + %res2 = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x4.256(<4 x float> %x0, <8 x float> %x2, i8 %mask) + %res3 = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x4.256(<4 x float> %x0, <8 x float> zeroinitializer, i8 %mask) + %res4 = fadd <8 x float> %res1, %res2 + %res5 = fadd <8 x float> %res3, %res4 + ret <8 x float> %res5 +} + +declare <8 x i32> @llvm.x86.avx512.mask.broadcasti32x4.256(<4 x i32>, <8 x i32>, i8) + +define <8 x i32>@test_int_x86_avx512_mask_broadcasti32x4_256(<4 x i32> %x0, <8 x i32> %x2, i8 %mask) { +; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x4_256: +; CHECK: kmovw %eax, %k1 +; CHECK: vshufi32x4 $0, %ymm0, %ymm0, %ymm2 {%k1} {z} +; CHECK: vshufi32x4 $0, %ymm0, %ymm0, %ymm1 {%k1} +; CHECK: vshufi32x4 $0, %ymm0, %ymm0, %ymm0 +; CHECK: vpaddd %ymm1, %ymm0, %ymm0 +; CHECK: vpaddd %ymm0, %ymm2, %ymm0 + + %res1 = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x4.256(<4 x i32> %x0, <8 x i32> %x2, i8 -1) + %res2 = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x4.256(<4 x i32> %x0, <8 x i32> %x2, i8 %mask) + %res3 = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x4.256(<4 x i32> %x0, <8 x i32> zeroinitializer, i8 %mask) + %res4 = add <8 x i32> %res1, %res2 + %res5 = add <8 x i32> %res3, %res4 + ret <8 x i32> %res5 +} -- 2.34.1