From 1b2932024f098a6968645ac78d5848951d877c19 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Thu, 12 Aug 2010 20:01:23 +0000 Subject: [PATCH] Remove trailing whitespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110944 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveInterval.h | 20 ++++----- include/llvm/CodeGen/LiveIntervalAnalysis.h | 16 +++---- lib/CodeGen/LiveInterval.cpp | 44 +++++++++--------- lib/CodeGen/LiveIntervalAnalysis.cpp | 50 ++++++++++----------- 4 files changed, 65 insertions(+), 65 deletions(-) diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h index f0e068b8e97..ff1dbc27752 100644 --- a/include/llvm/CodeGen/LiveInterval.h +++ b/include/llvm/CodeGen/LiveInterval.h @@ -39,7 +39,7 @@ namespace llvm { /// This class holds information about a machine level values, including /// definition and use points. /// - /// Care must be taken in interpreting the def index of the value. The + /// Care must be taken in interpreting the def index of the value. The /// following rules apply: /// /// If the isDefAccurate() method returns false then def does not contain the @@ -108,7 +108,7 @@ namespace llvm { /// For a stack interval, returns the reg which this stack interval was /// defined from. - /// For a register interval the behaviour of this method is undefined. + /// For a register interval the behaviour of this method is undefined. unsigned getReg() const { return cr.reg; } /// For a stack interval, set the defining register. /// This method should not be called on register intervals as it may lead @@ -189,7 +189,7 @@ namespace llvm { } /// containsRange - Return true if the given range, [S, E), is covered by - /// this range. + /// this range. bool containsRange(SlotIndex S, SlotIndex E) const { assert((S < E) && "Backwards interval?"); return (start <= S && S < end) && (start < E && E <= end); @@ -236,7 +236,7 @@ namespace llvm { float weight; // weight of this interval Ranges ranges; // the ranges in which this register is live VNInfoList valnos; // value#'s - + struct InstrSlots { enum { LOAD = 0, @@ -281,7 +281,7 @@ namespace llvm { while (I->end <= Pos) ++I; return I; } - + void clear() { valnos.clear(); ranges.clear(); @@ -305,7 +305,7 @@ namespace llvm { bool containsOneValue() const { return valnos.size() == 1; } unsigned getNumValNums() const { return (unsigned)valnos.size(); } - + /// getValNumInfo - Returns pointer to the specified val#. /// inline VNInfo *getValNumInfo(unsigned ValNo) { @@ -350,7 +350,7 @@ namespace llvm { } return true; } - + /// MergeValueNumberInto - This method is called when two value nubmers /// are found to be equivalent. This eliminates V1, replacing all /// LiveRanges with the V1 value number with the V2 value number. This can @@ -391,7 +391,7 @@ namespace llvm { /// except for the register of the interval. void Copy(const LiveInterval &RHS, MachineRegisterInfo *MRI, VNInfo::Allocator &VNInfoAllocator); - + bool empty() const { return ranges.empty(); } /// beginIndex - Return the lowest numbered slot covered by interval. @@ -458,14 +458,14 @@ namespace llvm { iterator FindLiveRangeContaining(SlotIndex Idx); /// findDefinedVNInfo - Find the by the specified - /// index (register interval) or defined + /// index (register interval) or defined VNInfo *findDefinedVNInfoForRegInt(SlotIndex Idx) const; /// findDefinedVNInfo - Find the VNInfo that's defined by the specified /// register (stack inteval only). VNInfo *findDefinedVNInfoForStackInt(unsigned Reg) const; - + /// overlaps - Return true if the intersection of the two live intervals is /// not empty. bool overlaps(const LiveInterval& other) const { diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index 04477acfaa4..2918c3c2abe 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -42,7 +42,7 @@ namespace llvm { class TargetInstrInfo; class TargetRegisterClass; class VirtRegMap; - + class LiveIntervals : public MachineFunctionPass { MachineFunction* mf_; MachineRegisterInfo* mri_; @@ -123,7 +123,7 @@ namespace llvm { unsigned getFuncInstructionCount() { return indexes_->getFunctionSize(); } - + /// getApproximateInstructionCount - computes an estimate of the number /// of instructions in a given LiveInterval. unsigned getApproximateInstructionCount(LiveInterval& I) { @@ -155,7 +155,7 @@ namespace llvm { /// dupInterval - Duplicate a live interval. The caller is responsible for /// managing the allocated memory. LiveInterval *dupInterval(LiveInterval *li); - + /// addLiveRangeToEndOfBlock - Given a register and an instruction, /// adds a live range from that instruction to the end of its MBB. LiveRange addLiveRangeToEndOfBlock(unsigned reg, @@ -187,7 +187,7 @@ namespace llvm { SlotIndex getInstructionIndex(const MachineInstr *instr) const { return indexes_->getInstructionIndex(instr); } - + /// Returns the instruction associated with the given index. MachineInstr* getInstructionFromIndex(SlotIndex index) const { return indexes_->getInstructionFromIndex(index); @@ -196,12 +196,12 @@ namespace llvm { /// Return the first index in the given basic block. SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const { return indexes_->getMBBStartIdx(mbb); - } + } /// Return the last index in the given basic block. SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const { return indexes_->getMBBEndIdx(mbb); - } + } bool isLiveInToMBB(const LiveInterval &li, const MachineBasicBlock *mbb) const { @@ -306,7 +306,7 @@ namespace llvm { /// within a single basic block. bool intervalIsInOneMBB(const LiveInterval &li) const; - private: + private: /// computeIntervals - Compute live intervals. void computeIntervals(); @@ -320,7 +320,7 @@ namespace llvm { /// isPartialRedef - Return true if the specified def at the specific index /// is partially re-defining the specified live interval. A common case of - /// this is a definition of the sub-register. + /// this is a definition of the sub-register. bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO, LiveInterval &interval); diff --git a/lib/CodeGen/LiveInterval.cpp b/lib/CodeGen/LiveInterval.cpp index 6820a615e8d..9a853e8eafa 100644 --- a/lib/CodeGen/LiveInterval.cpp +++ b/lib/CodeGen/LiveInterval.cpp @@ -309,7 +309,7 @@ LiveInterval::addRangeFrom(LiveRange LR, iterator From) { return ranges.insert(it, LR); } -/// isInOneLiveRange - Return true if the range specified is entirely in +/// isInOneLiveRange - Return true if the range specified is entirely in /// a single LiveRange of the live interval. bool LiveInterval::isInOneLiveRange(SlotIndex Start, SlotIndex End) { Ranges::iterator I = std::upper_bound(ranges.begin(), ranges.end(), Start); @@ -386,7 +386,7 @@ void LiveInterval::removeValNo(VNInfo *ValNo) { /// getLiveRangeContaining - Return the live range that contains the /// specified index, or null if there is none. -LiveInterval::const_iterator +LiveInterval::const_iterator LiveInterval::FindLiveRangeContaining(SlotIndex Idx) const { const_iterator It = std::upper_bound(begin(), end(), Idx); if (It != ranges.begin()) { @@ -398,7 +398,7 @@ LiveInterval::FindLiveRangeContaining(SlotIndex Idx) const { return end(); } -LiveInterval::iterator +LiveInterval::iterator LiveInterval::FindLiveRangeContaining(SlotIndex Idx) { iterator It = std::upper_bound(begin(), end(), Idx); if (It != begin()) { @@ -406,7 +406,7 @@ LiveInterval::FindLiveRangeContaining(SlotIndex Idx) { if (It->contains(Idx)) return It; } - + return end(); } @@ -438,11 +438,11 @@ VNInfo *LiveInterval::findDefinedVNInfoForStackInt(unsigned reg) const { /// the intervals are not joinable, this aborts. void LiveInterval::join(LiveInterval &Other, const int *LHSValNoAssignments, - const int *RHSValNoAssignments, + const int *RHSValNoAssignments, SmallVector &NewVNInfo, MachineRegisterInfo *MRI) { // Determine if any of our live range values are mapped. This is uncommon, so - // we want to avoid the interval scan if not. + // we want to avoid the interval scan if not. bool MustMapCurValNos = false; unsigned NumVals = getNumValNums(); unsigned NumNewVals = NewVNInfo.size(); @@ -462,7 +462,7 @@ void LiveInterval::join(LiveInterval &Other, ++OutIt; for (iterator I = OutIt, E = end(); I != E; ++I) { OutIt->valno = NewVNInfo[LHSValNoAssignments[I->valno->id]]; - + // If this live range has the same value # as its immediate predecessor, // and if they are neighbors, remove one LiveRange. This happens when we // have [0,3:0)[4,7:1) and map 0/1 onto the same value #. @@ -473,12 +473,12 @@ void LiveInterval::join(LiveInterval &Other, OutIt->start = I->start; OutIt->end = I->end; } - + // Didn't merge, on to the next one. ++OutIt; } } - + // If we merge some live ranges, chop off the end. ranges.erase(OutIt, end()); } @@ -496,7 +496,7 @@ void LiveInterval::join(LiveInterval &Other, if (VNI) { if (NumValNos >= NumVals) valnos.push_back(VNI); - else + else valnos[NumValNos] = VNI; VNI->id = NumValNos++; // Renumber val#. } @@ -521,7 +521,7 @@ void LiveInterval::join(LiveInterval &Other, /// interval as the specified value number. The LiveRanges in RHS are /// allowed to overlap with LiveRanges in the current interval, but only if /// the overlapping LiveRanges have the specified value number. -void LiveInterval::MergeRangesInAsValue(const LiveInterval &RHS, +void LiveInterval::MergeRangesInAsValue(const LiveInterval &RHS, VNInfo *LHSValNo) { // TODO: Make this more efficient. iterator InsertPos = begin(); @@ -570,7 +570,7 @@ void LiveInterval::MergeValueInAsValue( // If this trimmed away the whole range, ignore it. if (Start == End) continue; } - + // Map the valno in the other live range to the current live range. IP = addRangeFrom(LiveRange(Start, End, LHSValNo), IP); } @@ -585,7 +585,7 @@ void LiveInterval::MergeValueInAsValue( if (I->valno == V1) { isDead = false; break; - } + } if (isDead) { // Now that V1 is dead, remove it. markValNoForDeletion(V1); @@ -602,7 +602,7 @@ void LiveInterval::MergeInClobberRanges(LiveIntervals &li_, const LiveInterval &Clobbers, VNInfo::Allocator &VNInfoAllocator) { if (Clobbers.empty()) return; - + DenseMap ValNoMaps; VNInfo *UnusedValNo = 0; iterator IP = begin(); @@ -672,10 +672,10 @@ void LiveInterval::MergeInClobberRange(LiveIntervals &li_, // for unknown values, use it. VNInfo *ClobberValNo = getNextValue(li_.getInvalidIndex(), 0, false, VNInfoAllocator); - + iterator IP = begin(); IP = std::upper_bound(IP, end(), Start); - + // If the start of this range overlaps with an existing liverange, trim it. if (IP != begin() && IP[-1].end > Start) { Start = IP[-1].end; @@ -688,7 +688,7 @@ void LiveInterval::MergeInClobberRange(LiveIntervals &li_, // If this trimmed away the whole range, ignore it. if (Start == End) return; } - + // Insert the clobber interval. addRangeFrom(LiveRange(Start, End, ClobberValNo), IP); } @@ -715,7 +715,7 @@ VNInfo* LiveInterval::MergeValueNumberInto(VNInfo *V1, VNInfo *V2) { for (iterator I = begin(); I != end(); ) { iterator LR = I++; if (LR->valno != V1) continue; // Not a V1 LiveRange. - + // Okay, we found a V1 live range. If it had a previous, touching, V2 live // range, extend it. if (LR != begin()) { @@ -729,11 +729,11 @@ VNInfo* LiveInterval::MergeValueNumberInto(VNInfo *V1, VNInfo *V2) { LR = Prev; } } - + // Okay, now we have a V1 or V2 live range that is maximally merged forward. // Ensure that it is a V2 live-range. LR->valno = V2; - + // If we can merge it into later V2 live ranges, do so now. We ignore any // following V1 live ranges, as they will be merged in subsequent iterations // of the loop. @@ -745,10 +745,10 @@ VNInfo* LiveInterval::MergeValueNumberInto(VNInfo *V1, VNInfo *V2) { } } } - + // Now that V1 is dead, remove it. markValNoForDeletion(V1); - + return V2; } diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index a6dc3366519..21563c4f9a1 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -47,7 +47,7 @@ using namespace llvm; // Hidden options for help debugging. -static cl::opt DisableReMat("disable-rematerialization", +static cl::opt DisableReMat("disable-rematerialization", cl::init(false), cl::Hidden); STATISTIC(numIntervals , "Number of original intervals"); @@ -66,12 +66,12 @@ void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.addPreservedID(MachineLoopInfoID); AU.addPreservedID(MachineDominatorsID); - + if (!StrongPHIElim) { AU.addPreservedID(PHIEliminationID); AU.addRequiredID(PHIEliminationID); } - + AU.addRequiredID(TwoAddressInstructionPassID); AU.addPreserved(); AU.addRequired(); @@ -85,7 +85,7 @@ void LiveIntervals::releaseMemory() { for (DenseMap::iterator I = r2iMap_.begin(), E = r2iMap_.end(); I != E; ++I) delete I->second; - + r2iMap_.clear(); // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd. @@ -275,7 +275,7 @@ bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) { /// isPartialRedef - Return true if the specified def at the specific index is /// partially re-defining the specified live interval. A common case of this is -/// a definition of the sub-register. +/// a definition of the sub-register. bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO, LiveInterval &interval) { if (!MO.getSubReg() || MO.isEarlyClobber()) @@ -415,8 +415,8 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, // def-and-use register operand. // It may also be partial redef like this: - // 80 %reg1041:6 = VSHRNv4i16 %reg1034, 12, pred:14, pred:%reg0 - // 120 %reg1041:5 = VSHRNv4i16 %reg1039, 12, pred:14, pred:%reg0 + // 80 %reg1041:6 = VSHRNv4i16 %reg1034, 12, pred:14, pred:%reg0 + // 120 %reg1041:5 = VSHRNv4i16 %reg1039, 12, pred:14, pred:%reg0 bool PartReDef = isPartialRedef(MIIdx, MO, interval); if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) { // If this is a two-address definition, then we have already processed @@ -451,7 +451,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, // A re-def may be a copy. e.g. %reg1030:6 = VMOVD %reg1026, ... if (PartReDef && mi->isCopyLike()) OldValNo->setCopy(&*mi); - + // Add the new live interval which replaces the range for the input copy. LiveRange LR(DefIndex, RedefIndex, ValNo); DEBUG(dbgs() << " replace range with " << LR); @@ -481,7 +481,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, if (mi->isCopyLike()) CopyMI = mi; ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator); - + SlotIndex killIndex = getMBBEndIdx(mbb); LiveRange LR(defIndex, killIndex, ValNo); interval.addRange(LR); @@ -558,10 +558,10 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, goto exit; } } - + baseIndex = baseIndex.getNextIndex(); } - + // The only case we should have a dead physreg here without a killing or // instruction where we know it's dead is if it is live-in to the function // and never used. Another possible case is the implicit use of the @@ -685,7 +685,7 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB, /// registers. for some ordering of the machine instructions [1,N] a /// live interval is an interval [i, j) where 1 <= i <= j < N for /// which a variable is live -void LiveIntervals::computeIntervals() { +void LiveIntervals::computeIntervals() { DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n" << "********** Function: " << ((Value*)mf_->getFunction())->getName() << '\n'); @@ -712,11 +712,11 @@ void LiveIntervals::computeIntervals() { handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS), true); } - + // Skip over empty initial indices. if (getInstructionFromIndex(MIIndex) == 0) MIIndex = indexes_->getNextNonNullIndex(MIIndex); - + for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end(); MI != miEnd; ++MI) { DEBUG(dbgs() << MIIndex << "\t" << *MI); @@ -735,7 +735,7 @@ void LiveIntervals::computeIntervals() { else if (MO.isUndef()) UndefUses.push_back(MO.getReg()); } - + // Move to the next instr slot. MIIndex = indexes_->getNextNonNullIndex(MIIndex); } @@ -780,7 +780,7 @@ unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li, unsigned Reg = MO.getReg(); if (Reg == 0 || Reg == li.reg) continue; - + if (TargetRegisterInfo::isPhysicalRegister(Reg) && !allocatableRegs_[Reg]) continue; @@ -799,7 +799,7 @@ unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li, /// which reaches the given instruction also reaches the specified use index. bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI, SlotIndex UseIdx) const { - SlotIndex Index = getInstructionIndex(MI); + SlotIndex Index = getInstructionIndex(MI); VNInfo *ValNo = li.FindLiveRangeContaining(Index)->valno; LiveInterval::const_iterator UI = li.FindLiveRangeContaining(UseIdx); return UI != li.end() && UI->valno == ValNo; @@ -904,7 +904,7 @@ static bool FilterFoldedOps(MachineInstr *MI, } return false; } - + /// tryFoldMemoryOperand - Attempts to fold either a spill / restore from /// slot / to reg or any rematerialized load into ith operand of specified @@ -1024,7 +1024,7 @@ void LiveIntervals::rewriteImplicitOps(const LiveInterval &li, /// for addIntervalsForSpills to rewrite uses / defs for the given live range. bool LiveIntervals:: rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, - bool TrySplit, SlotIndex index, SlotIndex end, + bool TrySplit, SlotIndex index, SlotIndex end, MachineInstr *MI, MachineInstr *ReMatOrigDefMI, MachineInstr *ReMatDefMI, unsigned Slot, int LdSlot, @@ -1083,7 +1083,7 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, // keep the src/dst regs pinned. // // Keep track of whether we replace a use and/or def so that we can - // create the spill interval with the appropriate range. + // create the spill interval with the appropriate range. SmallVector Ops; tie(HasUse, HasDef) = MI->readsWritesVirtualRegister(Reg, &Ops); @@ -1145,7 +1145,7 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, if (mopj.isImplicit()) rewriteImplicitOps(li, MI, NewVReg, vrm); } - + if (CreatedNewVReg) { if (DefIsReMat) { vrm.setVirtIsReMaterialized(NewVReg, ReMatDefMI); @@ -1685,7 +1685,7 @@ addIntervalsForSpills(const LiveInterval &li, if (NeedStackSlot && vrm.getPreSplitReg(li.reg) == 0) { if (vrm.getStackSlot(li.reg) == VirtRegMap::NO_STACK_SLOT) Slot = vrm.assignVirt2StackSlot(li.reg); - + // This case only occurs when the prealloc splitter has already assigned // a stack slot to this vreg. else @@ -1742,7 +1742,7 @@ addIntervalsForSpills(const LiveInterval &li, Ops.push_back(j); if (MO.isDef()) continue; - if (isReMat || + if (isReMat || (!FoundUse && !alsoFoldARestore(Id, index, VReg, RestoreMBBs, RestoreIdxes))) { // MI has two-address uses of the same register. If the use @@ -1887,7 +1887,7 @@ bool LiveIntervals::hasAllocatableSuperReg(unsigned Reg) const { /// getRepresentativeReg - Find the largest super register of the specified /// physical register. unsigned LiveIntervals::getRepresentativeReg(unsigned Reg) const { - // Find the largest super-register that is allocatable. + // Find the largest super-register that is allocatable. unsigned BestReg = Reg; for (const unsigned* AS = tri_->getSuperRegisters(Reg); *AS; ++AS) { unsigned SuperReg = *AS; @@ -2001,7 +2001,7 @@ LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg, SlotIndex(getInstructionIndex(startInst).getDefIndex()), getMBBEndIdx(startInst->getParent()), VN); Interval.addRange(LR); - + return LR; } -- 2.34.1