From 1ba1a1f573d321913629ee65cdcde7b18e92febc Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 14 Mar 2016 16:01:59 +0800 Subject: [PATCH] UPSTREAM: clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on rk3036 The emac needs constant and very specific rate but the possible PLL-sources are very limited, so we expect the PLL source to be set manually on per board and don't want it to get changed in an automatic way later. So add the necessary clock-id and disable reparenting on set_rate calls. Change-Id: I999ba51df51fef50075eb119e3b976b990fe714c Signed-off-by: Heiko Stuebner Cc: Michael Turquette Cc: Heiko Stuebner Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Signed-off-by: Caesar Wang Signed-off-by: David S. Miller (cherry picked from git.kernel.org next/linux-next.git master commit 2c6fae2501d87ca94b5249df38797f02d4e39add) --- drivers/clk/rockchip/clk-rk3036.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index 82b6e4458df5..3aa789dfcea1 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -346,7 +346,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS, RK2928_CLKGATE_CON(10), 5, GFLAGS), - COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0, + COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT, RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(21), 3, 1, MFLAGS), -- 2.34.1