From 1cb0acee8ae0b802f9689d7145cdbfcb652965f0 Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Fri, 8 May 2009 18:50:26 +0000
Subject: [PATCH] Add 8 bit select

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71235 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/MSP430/MSP430InstrInfo.td | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td
index 021e8bbeefc..93f5c09db12 100644
--- a/lib/Target/MSP430/MSP430InstrInfo.td
+++ b/lib/Target/MSP430/MSP430InstrInfo.td
@@ -107,6 +107,10 @@ def ADJCALLSTACKUP   : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
 }
 
 let usesCustomDAGSchedInserter = 1 in {
+  def Select8  : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cc),
+                        "# Select8 PSEUDO",
+                        [(set GR8:$dst,
+                          (MSP430selectcc GR8:$src1, GR8:$src2, imm:$cc))]>;
   def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cc),
                         "# Select16 PSEUDO",
                         [(set GR16:$dst,
-- 
2.34.1