From 1cda5a3a283fc2cdaaa838a535c207c037376316 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E5=BC=A0=E6=99=B4?= Date: Sat, 12 Jul 2014 12:52:39 +0800 Subject: [PATCH] rk3036:clk:modify init clocks --- arch/arm/boot/dts/rk3036-clocks.dtsi | 10 ++++++---- arch/arm/boot/dts/rk3036.dtsi | 2 +- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/rk3036-clocks.dtsi b/arch/arm/boot/dts/rk3036-clocks.dtsi index 9b48f81ee543..95e06abf3177 100755 --- a/arch/arm/boot/dts/rk3036-clocks.dtsi +++ b/arch/arm/boot/dts/rk3036-clocks.dtsi @@ -85,7 +85,7 @@ fixed_factor_cons { compatible = "rockchip,rk-fixed-factor-cons"; - +/* otgphy0_12m: otgphy0_12m { compatible = "rockchip,rk-fixed-factor-clock"; clocks = <&clk_gates1 5>; @@ -94,7 +94,7 @@ clock-mult = <20>; #clock-cells = <0>; }; - +*/ hclk_vcodec: hclk_vcodec { compatible = "rockchip,rk-fixed-factor-clock"; clocks = <&aclk_vcodec_pre>; @@ -822,6 +822,7 @@ #clock-cells = <0>; rockchip,clkops-idx = ; + rockchip,flags = ; }; /* reg[31:7]: reserved */ @@ -939,7 +940,7 @@ clk_ddr: ddr_clk_pll_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 1>; - clocks = <&clk_gates0 2>, <&clk_gates0 8>; + clocks = <&clk_dpll>, <&dummy>; clock-output-names = "clk_ddr"; #clock-cells = <0>; }; @@ -1078,6 +1079,7 @@ #clock-cells = <0>; rockchip,clkops-idx = ; + rockchip,flags = ; }; /* reg[13]: reserved */ @@ -1115,7 +1117,7 @@ clk_gpu_pre: clk_gpu_pre_mux { compatible = "rockchip,rk3188-mux-con"; rockchip,bits = <8 2>; - clocks = <&dummy>, <&clk_dpll>, <&clk_gpll>; + clocks = <&dummy>, <&dummy>, <&clk_gpll>; clock-output-names = "clk_gpu_pre"; #clock-cells = <0>; #clock-init-cells = <1>; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index e267b651b6bb..4180765ff889 100755 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -196,7 +196,7 @@ <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>, <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>, <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>, - <&clk_mac_pll &clk_apll>; + <&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>; rockchip,clocks-init-rate = <&clk_core 816000000>, <&clk_gpll 594000000>, <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>, -- 2.34.1