From 1cff40819c2d623e74d04f195e3c1dbbe3c35f39 Mon Sep 17 00:00:00 2001
From: Reid Spencer
Date: Fri, 20 Jul 2007 20:03:33 +0000
Subject: [PATCH] Silly HTML
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40117 91177308-0d34-0410-b5e6-96231b3b80d8
---
docs/LangRef.html | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/docs/LangRef.html b/docs/LangRef.html
index fa7fefafc47..a45aba896b3 100644
--- a/docs/LangRef.html
+++ b/docs/LangRef.html
@@ -5078,13 +5078,13 @@ declare void @llvm.memory.barrier( i1 <ll>, i1 <ls>, i1 <sl>,
The llvm.memory.barrier intrinsic requires four boolean arguments.
Each argument enables a specific barrier as listed below.
+
- ll: load-load barrier
- ls: load-store barrier
- sl: store-load barrier
- ss: store-store barrier
-
Semantics:
This intrinsic causes the system to enforce some ordering constraints upon
@@ -5094,6 +5094,7 @@ declare void @llvm.memory.barrier( i1 <ll>, i1 <ls>, i1 <sl>,
(f.ex. load-load, or store-load), all of the first operations preceding the
barrier will complete before any of the second operations succeeding the
barrier begin. Specifically the semantics for each pairing is as follows:
+
- ll: All loads before the barrier must complete before any load
after the barrier begins.
@@ -5104,6 +5105,7 @@ declare void @llvm.memory.barrier( i1 <ll>, i1 <ls>, i1 <sl>,
- sl: All stores before the barrier must complete before any
load after the barrier begins.
+
These semantics are applied with a logical "and" behavior when more than one
is enabled in a single memory barrier intrinsic.
--
2.34.1