From 1f4a0a8c6fc33d7850f8f826d951d1670bfeb2d8 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Sat, 4 Dec 2010 16:30:32 +0800 Subject: [PATCH] rk29: clock: add set rate for aclk_periph/hclk_periph/pclk_periph --- arch/arm/mach-rk29/clock.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-rk29/clock.c b/arch/arm/mach-rk29/clock.c index bd4735e1ec08..202d83a6dac0 100755 --- a/arch/arm/mach-rk29/clock.c +++ b/arch/arm/mach-rk29/clock.c @@ -545,6 +545,7 @@ static struct clk hclk_cpu = { .name = "hclk_cpu", .parent = &aclk_cpu, .recalc = clksel_recalc_shift, + .set_rate = clksel_set_rate_shift, .clksel_con = CRU_CLKSEL0_CON, .clksel_mask = 3, .clksel_shift = 8, @@ -555,6 +556,7 @@ static struct clk pclk_cpu = { .name = "pclk_cpu", .parent = &aclk_cpu, .recalc = clksel_recalc_shift, + .set_rate = clksel_set_rate_shift, .clksel_con = CRU_CLKSEL0_CON, .clksel_mask = 3, .clksel_shift = 10, @@ -567,6 +569,7 @@ static struct clk aclk_periph = { .gate_idx = CLK_GATE_PEIRPH_AXI, .parent = &periph_pll_clk, .recalc = clksel_recalc_div, + .set_rate = clksel_set_rate_div, .clksel_con = CRU_CLKSEL0_CON, .clksel_mask = 0x1F, .clksel_shift = 14, @@ -578,6 +581,7 @@ static struct clk pclk_periph = { .gate_idx = CLK_GATE_PEIRPH_APB, .parent = &aclk_periph, .recalc = clksel_recalc_shift, + .set_rate = clksel_set_rate_shift, .clksel_con = CRU_CLKSEL0_CON, .clksel_mask = 3, .clksel_shift = 19, @@ -590,6 +594,7 @@ static struct clk hclk_periph = { .gate_idx = CLK_GATE_PEIRPH_AHB, .parent = &aclk_periph, .recalc = clksel_recalc_shift, + .set_rate = clksel_set_rate_shift, .clksel_con = CRU_CLKSEL0_CON, .clksel_mask = 3, .clksel_shift = 21, -- 2.34.1