From 1fb22447a51c243733c024cef573643dd0f431e3 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=E9=BB=84=E6=B6=9B?= <huangtao@rock-chips.com>
Date: Tue, 14 Aug 2012 17:29:10 +0800
Subject: [PATCH] rk30: cru: fix typo, PEIRPH -> PERIPH

---
 arch/arm/mach-rk30/clock_data.c       |  8 ++++----
 arch/arm/mach-rk30/include/mach/cru.h |  8 ++++----
 arch/arm/mach-rk30/pm.c               | 22 +++++++++++-----------
 3 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-rk30/clock_data.c b/arch/arm/mach-rk30/clock_data.c
index 7579235ebabd..e28a2df3f528 100644
--- a/arch/arm/mach-rk30/clock_data.c
+++ b/arch/arm/mach-rk30/clock_data.c
@@ -1521,7 +1521,7 @@ static struct clk aclk_periph = {
 	.name		= "aclk_periph",
 	.parent		= &general_pll_clk,
 	.mode		= gate_mode,
-	.gate_idx	= CLK_GATE_ACLK_PEIRPH,
+	.gate_idx	= CLK_GATE_ACLK_PERIPH,
 	.recalc		= clksel_recalc_div,
 	.set_rate	= clksel_set_rate_freediv,
 	.clksel_con	= CRU_CLKSELS_CON(10),
@@ -1529,13 +1529,13 @@ static struct clk aclk_periph = {
 	CRU_SRC_SET(1,15),
 	CRU_PARENTS_SET(aclk_periph_parents),
 };
-GATE_CLK(periph_src, aclk_periph, PEIRPH_SRC);
+GATE_CLK(periph_src, aclk_periph, PERIPH_SRC);
 
 static struct clk pclk_periph = {
 	.name		= "pclk_periph",
 	.parent		= &aclk_periph,
 	.mode		= gate_mode,
-	.gate_idx	= CLK_GATE_PCLK_PEIRPH,
+	.gate_idx	= CLK_GATE_PCLK_PERIPH,
 	.recalc		= clksel_recalc_shift,
 	.set_rate	= clksel_set_rate_shift,
  	.clksel_con	= CRU_CLKSELS_CON(10),
@@ -1546,7 +1546,7 @@ static struct clk hclk_periph = {
 	.name		= "hclk_periph",
 	.parent		= &aclk_periph,
 	.mode		= gate_mode,
-	.gate_idx	= CLK_GATE_HCLK_PEIRPH,
+	.gate_idx	= CLK_GATE_HCLK_PERIPH,
 	.recalc		= clksel_recalc_shift,
 	.set_rate	= clksel_set_rate_shift,
 	.clksel_con = CRU_CLKSELS_CON(10),
diff --git a/arch/arm/mach-rk30/include/mach/cru.h b/arch/arm/mach-rk30/include/mach/cru.h
index c0e809c69036..113af41c2181 100755
--- a/arch/arm/mach-rk30/include/mach/cru.h
+++ b/arch/arm/mach-rk30/include/mach/cru.h
@@ -210,10 +210,10 @@ enum cru_clk_gate {
 	CLK_GATE_UART3,
 	CLK_GATE_FRAC_UART3,
 
-	CLK_GATE_PEIRPH_SRC = CLK_GATE_CLKID(2),
-	CLK_GATE_ACLK_PEIRPH,
-	CLK_GATE_HCLK_PEIRPH,
-	CLK_GATE_PCLK_PEIRPH,
+	CLK_GATE_PERIPH_SRC = CLK_GATE_CLKID(2),
+	CLK_GATE_ACLK_PERIPH,
+	CLK_GATE_HCLK_PERIPH,
+	CLK_GATE_PCLK_PERIPH,
 	CLK_GATE_SMC,
 	CLK_GATE_MAC,
 	CLK_GATE_HSADC,
diff --git a/arch/arm/mach-rk30/pm.c b/arch/arm/mach-rk30/pm.c
index 464667b9e587..1463afca801b 100644
--- a/arch/arm/mach-rk30/pm.c
+++ b/arch/arm/mach-rk30/pm.c
@@ -42,13 +42,13 @@ void __sramfunc sram_printch(char byte)
 	u32 clk_gate2, clk_gate4, clk_gate8;
 
 	gate_save_soc_clk(0
-			  | (1 << CLK_GATE_ACLK_PEIRPH % 16)
-			  | (1 << CLK_GATE_HCLK_PEIRPH % 16)
-			  | (1 << CLK_GATE_PCLK_PEIRPH % 16)
+			  | (1 << CLK_GATE_ACLK_PERIPH % 16)
+			  | (1 << CLK_GATE_HCLK_PERIPH % 16)
+			  | (1 << CLK_GATE_PCLK_PERIPH % 16)
 			  , clk_gate2, CRU_CLKGATES_CON(2), 0
-			  | (1 << ((CLK_GATE_ACLK_PEIRPH % 16) + 16))
-			  | (1 << ((CLK_GATE_HCLK_PEIRPH % 16) + 16))
-			  | (1 << ((CLK_GATE_PCLK_PEIRPH % 16) + 16)));
+			  | (1 << ((CLK_GATE_ACLK_PERIPH % 16) + 16))
+			  | (1 << ((CLK_GATE_HCLK_PERIPH % 16) + 16))
+			  | (1 << ((CLK_GATE_PCLK_PERIPH % 16) + 16)));
 	gate_save_soc_clk((1 << CLK_GATE_ACLK_CPU_PERI % 16)
 			  , clk_gate4, CRU_CLKGATES_CON(4),
 			  (1 << ((CLK_GATE_ACLK_CPU_PERI % 16) + 16)));
@@ -375,8 +375,8 @@ static void __sramfunc rk30_sram_suspend(void)
 	gate_save_soc_clk(0, clkgt_regs[1], CRU_CLKGATES_CON(1), 0xffff);
 	if(clkgt_regs[8]&((1<<12)|(1<13))){
 		gate_save_soc_clk(0
-				  | (1 << CLK_GATE_PEIRPH_SRC % 16)
-				  | (1 << CLK_GATE_PCLK_PEIRPH % 16)
+				  | (1 << CLK_GATE_PERIPH_SRC % 16)
+				  | (1 << CLK_GATE_PCLK_PERIPH % 16)
 				, clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
 	}else{
 		gate_save_soc_clk(0
@@ -489,9 +489,9 @@ static int rk30_pm_enter(suspend_state_t state)
 			  | (1 << CLK_GATE_DDR_GPLL % 16)
 			  , clkgt_regs[1], CRU_CLKGATES_CON(1), 0xffff);
 	gate_save_soc_clk(0
-			  | (1 << CLK_GATE_PEIRPH_SRC % 16)
-			  | (1 << CLK_GATE_PCLK_PEIRPH % 16)
-			  | (1 << CLK_GATE_ACLK_PEIRPH % 16)
+			  | (1 << CLK_GATE_PERIPH_SRC % 16)
+			  | (1 << CLK_GATE_PCLK_PERIPH % 16)
+			  | (1 << CLK_GATE_ACLK_PERIPH % 16)
 			  , clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff);
 	gate_save_soc_clk(0, clkgt_regs[3], CRU_CLKGATES_CON(3), 0xff9f);
 	gate_save_soc_clk(0
-- 
2.34.1