From 1fc6d8837f03471b815a9312091b9432939b49fc Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Wed, 13 Oct 2010 00:38:07 +0000 Subject: [PATCH] Add VCMPZ and VABS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116383 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrVFP.td | 83 ++++++++++++++++++++----------- test/MC/ARM/simple-fp-encoding.ll | 36 ++++++++++++++ 2 files changed, 91 insertions(+), 28 deletions(-) diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index d18c23c3161..17499106abb 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -175,27 +175,28 @@ class ADuI_Encode opcod1, bits<2> opcod2, bits<4> opcod3, let Inst{22} = Dd{4}; } -class ASuI_Encode opcod1, bits<2> opcod2, bits<4> opcod3, - bits<2> opcod4, bit opcod5, dag oops, dag iops, - InstrItinClass itin, string opc, string asm, +class ASbI_Encode opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, + dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : ASuI { + : ASbI { // Instruction operands. bits<5> Sd; + bits<5> Sn; bits<5> Sm; // Encode instruction operands. let Inst{3-0} = Sm{4-1}; let Inst{5} = Sm{0}; + let Inst{19-16} = Sn{4-1}; + let Inst{7} = Sn{0}; let Inst{15-12} = Sd{4-1}; let Inst{22} = Sd{0}; } -class ASbI_Encode opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, - dag iops, InstrItinClass itin, string opc, string asm, - list pattern> - : ASbI { +class ASbIn_Encode opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, + dag iops, InstrItinClass itin, string opc, string asm, + list pattern> + : ASbIn { // Instruction operands. bits<5> Sd; bits<5> Sn; @@ -210,20 +211,36 @@ class ASbI_Encode opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, let Inst{22} = Sd{0}; } -class ASbIn_Encode opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, - dag iops, InstrItinClass itin, string opc, string asm, +class ASuI_Encode opcod1, bits<2> opcod2, bits<4> opcod3, + bits<2> opcod4, bit opcod5, dag oops, dag iops, + InstrItinClass itin, string opc, string asm, + list pattern> + : ASuI { + // Instruction operands. + bits<5> Sd; + bits<5> Sm; + + // Encode instruction operands. + let Inst{3-0} = Sm{4-1}; + let Inst{5} = Sm{0}; + let Inst{15-12} = Sd{4-1}; + let Inst{22} = Sd{0}; +} + +class ASuIn_Encode opcod1, bits<2> opcod2, bits<4> opcod3, + bits<2> opcod4, bit opcod5, dag oops, dag iops, + InstrItinClass itin, string opc, string asm, list pattern> - : ASbIn { + : ASuIn { // Instruction operands. bits<5> Sd; - bits<5> Sn; bits<5> Sm; // Encode instruction operands. let Inst{3-0} = Sm{4-1}; let Inst{5} = Sm{0}; - let Inst{19-16} = Sn{4-1}; - let Inst{7} = Sn{0}; let Inst{15-12} = Sd{4-1}; let Inst{22} = Sd{0}; } @@ -313,27 +330,37 @@ def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins SPR:$a, SPR:$b), // FP Unary Operations. // -def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, (outs DPR:$dst), (ins DPR:$a), - IIC_fpUNA64, "vabs", ".f64\t$dst, $a", - [(set DPR:$dst, (fabs (f64 DPR:$a)))]>; +def VABSD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b11, 0, + (outs DPR:$Dd), (ins DPR:$Dm), + IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", + [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; -def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,(outs SPR:$dst), (ins SPR:$a), - IIC_fpUNA32, "vabs", ".f32\t$dst, $a", - [(set SPR:$dst, (fabs SPR:$a))]>; +def VABSS : ASuIn_Encode<0b11101, 0b11, 0b0000, 0b11, 0, + (outs SPR:$Sd), (ins SPR:$Sm), + IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", + [(set SPR:$Sd, (fabs SPR:$Sm))]>; let Defs = [FPSCR] in { -def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, (outs), (ins DPR:$a), - IIC_fpCMP64, "vcmpe", ".f64\t$a, #0", - [(arm_cmpfp0 (f64 DPR:$a))]>; +def VCMPEZD : ADuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0, + (outs), (ins DPR:$Dd), + IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", + [(arm_cmpfp0 (f64 DPR:$Dd))]> { + let Inst{3-0} = 0b0000; + let Inst{5} = 0; +} + +def VCMPEZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0, + (outs), (ins SPR:$Sd), + IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", + [(arm_cmpfp0 SPR:$Sd)]> { + let Inst{3-0} = 0b0000; + let Inst{5} = 0; +} def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins DPR:$a), IIC_fpCMP64, "vcmp", ".f64\t$a, #0", [/* For disassembly only; pattern left blank */]>; -def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, (outs), (ins SPR:$a), - IIC_fpCMP32, "vcmpe", ".f32\t$a, #0", - [(arm_cmpfp0 SPR:$a)]>; - def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins SPR:$a), IIC_fpCMP32, "vcmp", ".f32\t$a, #0", [/* For disassembly only; pattern left blank */]>; diff --git a/test/MC/ARM/simple-fp-encoding.ll b/test/MC/ARM/simple-fp-encoding.ll index bbd2e1e4c3d..7c3ec9e9021 100644 --- a/test/MC/ARM/simple-fp-encoding.ll +++ b/test/MC/ARM/simple-fp-encoding.ll @@ -104,3 +104,39 @@ entry: %cmp = fcmp oeq float %a, %b ret i1 %cmp } + +define i1 @f13(double %a) nounwind readnone { +entry: +; CHECK: f13 +; CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee] + %cmp = fcmp oeq double %a, 0.000000e+00 + ret i1 %cmp +} + +define i1 @f14(float %a) nounwind readnone { +entry: +; CHECK: f14 +; CHECK: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee] + %cmp = fcmp oeq float %a, 0.000000e+00 + ret i1 %cmp +} + +define double @f15(double %a) nounwind { +entry: +; CHECK: f15 +; CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee] + %call = tail call double @fabsl(double %a) + ret double %call +} + +declare double @fabsl(double) + +define float @f16(float %a) nounwind { +entry: +; CHECK: f16 +; This call generates a "bfc" instruction instead of "vabs.f32". + %call = tail call float @fabsf(float %a) + ret float %call +} + +declare float @fabsf(float) -- 2.34.1