From 2015236dfcd40f0b93e7d9f6dc4c380dc88bf3c0 Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard@amd.com>
Date: Mon, 16 Jul 2012 14:17:19 +0000
Subject: [PATCH] test/CodeGen/R600: Add some basic tests v6

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160273 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/R600/fadd.ll                    |  15 +++++++++++++++
 test/CodeGen/R600/fadd.ll.check              | Bin 0 -> 48 bytes
 test/CodeGen/R600/fmul.ll                    |  15 +++++++++++++++
 test/CodeGen/R600/fmul.ll.check              | Bin 0 -> 48 bytes
 test/CodeGen/R600/fsub.ll                    |  15 +++++++++++++++
 test/CodeGen/R600/fsub.ll.check              | Bin 0 -> 96 bytes
 test/CodeGen/R600/lit.local.cfg              |  13 +++++++++++++
 test/CodeGen/R600/llvm.AMDGPU.cos.ll         |  15 +++++++++++++++
 test/CodeGen/R600/llvm.AMDGPU.cos.ll.check   | Bin 0 -> 144 bytes
 test/CodeGen/R600/llvm.AMDGPU.floor.ll       |  15 +++++++++++++++
 test/CodeGen/R600/llvm.AMDGPU.floor.ll.check | Bin 0 -> 48 bytes
 test/CodeGen/R600/llvm.AMDGPU.mul.ll         |  16 ++++++++++++++++
 test/CodeGen/R600/llvm.AMDGPU.mul.ll.check   | Bin 0 -> 48 bytes
 test/CodeGen/R600/llvm.AMDGPU.pow.ll         |  16 ++++++++++++++++
 test/CodeGen/R600/llvm.AMDGPU.pow.ll.check   | Bin 0 -> 144 bytes
 test/CodeGen/R600/llvm.AMDGPU.rcp.ll         |  15 +++++++++++++++
 test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check   | Bin 0 -> 48 bytes
 test/CodeGen/R600/llvm.AMDGPU.sin.ll         |  15 +++++++++++++++
 test/CodeGen/R600/llvm.AMDGPU.sin.ll.check   | Bin 0 -> 144 bytes
 test/CodeGen/R600/llvm.AMDGPU.trunc.ll       |  15 +++++++++++++++
 test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check | Bin 0 -> 48 bytes
 test/CodeGen/R600/llvm.AMDIL.fabs..ll        |  15 +++++++++++++++
 test/CodeGen/R600/llvm.AMDIL.fabs..ll.check  | Bin 0 -> 48 bytes
 test/CodeGen/R600/llvm.AMDIL.max..ll         |  16 ++++++++++++++++
 test/CodeGen/R600/llvm.AMDIL.max..ll.check   | Bin 0 -> 48 bytes
 test/CodeGen/R600/llvm.AMDIL.min..ll         |  16 ++++++++++++++++
 test/CodeGen/R600/llvm.AMDIL.min..ll.check   | Bin 0 -> 48 bytes
 27 files changed, 212 insertions(+)
 create mode 100644 test/CodeGen/R600/fadd.ll
 create mode 100644 test/CodeGen/R600/fadd.ll.check
 create mode 100644 test/CodeGen/R600/fmul.ll
 create mode 100644 test/CodeGen/R600/fmul.ll.check
 create mode 100644 test/CodeGen/R600/fsub.ll
 create mode 100644 test/CodeGen/R600/fsub.ll.check
 create mode 100644 test/CodeGen/R600/lit.local.cfg
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.cos.ll
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.cos.ll.check
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.floor.ll
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.floor.ll.check
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.mul.ll
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.mul.ll.check
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.pow.ll
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.pow.ll.check
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.rcp.ll
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.sin.ll
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.sin.ll.check
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.trunc.ll
 create mode 100644 test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check
 create mode 100644 test/CodeGen/R600/llvm.AMDIL.fabs..ll
 create mode 100644 test/CodeGen/R600/llvm.AMDIL.fabs..ll.check
 create mode 100644 test/CodeGen/R600/llvm.AMDIL.max..ll
 create mode 100644 test/CodeGen/R600/llvm.AMDIL.max..ll.check
 create mode 100644 test/CodeGen/R600/llvm.AMDIL.min..ll
 create mode 100644 test/CodeGen/R600/llvm.AMDIL.min..ll.check

diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll
new file mode 100644
index 00000000000..874fcc6f43e
--- /dev/null
+++ b/test/CodeGen/R600/fadd.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = fadd float %r0, %r1
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
diff --git a/test/CodeGen/R600/fadd.ll.check b/test/CodeGen/R600/fadd.ll.check
new file mode 100644
index 0000000000000000000000000000000000000000..886082f22622bf687d2a9c53214873c3691f7620
GIT binary patch
literal 48
TcmZQzKn9G+90VIA43z=^0Av6J

literal 0
HcmV?d00001

diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll
new file mode 100644
index 00000000000..28bc4d8008e
--- /dev/null
+++ b/test/CodeGen/R600/fmul.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = fmul float %r0, %r1
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
diff --git a/test/CodeGen/R600/fmul.ll.check b/test/CodeGen/R600/fmul.ll.check
new file mode 100644
index 0000000000000000000000000000000000000000..9ba36ccb7416ea5886d596684ff4bf8bc3759d07
GIT binary patch
literal 48
VcmZQzKn9G+90Z$@fr$Ys1pokc00sa6

literal 0
HcmV?d00001

diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll
new file mode 100644
index 00000000000..8e431280fca
--- /dev/null
+++ b/test/CodeGen/R600/fsub.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = fsub float %r0, %r1
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
diff --git a/test/CodeGen/R600/fsub.ll.check b/test/CodeGen/R600/fsub.ll.check
new file mode 100644
index 0000000000000000000000000000000000000000..79993541ce6ba84501876e488bfd428501f1383f
GIT binary patch
literal 96
fcmZQzU|?iqzzY}|7#Spi7z@BE2s9C>6e<M(2aNzC

literal 0
HcmV?d00001

diff --git a/test/CodeGen/R600/lit.local.cfg b/test/CodeGen/R600/lit.local.cfg
new file mode 100644
index 00000000000..79fc2ba362f
--- /dev/null
+++ b/test/CodeGen/R600/lit.local.cfg
@@ -0,0 +1,13 @@
+config.suffixes = ['.ll', '.c', '.cpp']
+
+def getRoot(config):
+    if not config.parent:
+        return config
+    return getRoot(config.parent)
+
+root = getRoot(config)
+
+targets = set(root.targets_to_build.split())
+if not 'AMDGPU' in targets:
+    config.unsupported = True
+
diff --git a/test/CodeGen/R600/llvm.AMDGPU.cos.ll b/test/CodeGen/R600/llvm.AMDGPU.cos.ll
new file mode 100644
index 00000000000..8db95638aeb
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.cos.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.AMDGPU.cos( float %r0)
+   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.cos(float ) readnone
diff --git a/test/CodeGen/R600/llvm.AMDGPU.cos.ll.check b/test/CodeGen/R600/llvm.AMDGPU.cos.ll.check
new file mode 100644
index 0000000000000000000000000000000000000000..ef1389b27a373ab51fe211f04b756719685581c4
GIT binary patch
literal 144
scmZSh%K!$=Kb7ntEDVy7fssKHh+zQ1f{CEhARUBNA#^b^^ug2v0Ge|HiU0rr

literal 0
HcmV?d00001

diff --git a/test/CodeGen/R600/llvm.AMDGPU.floor.ll b/test/CodeGen/R600/llvm.AMDGPU.floor.ll
new file mode 100644
index 00000000000..729a7834773
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.floor.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.AMDGPU.floor( float %r0)
+   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.floor(float ) readnone
diff --git a/test/CodeGen/R600/llvm.AMDGPU.floor.ll.check b/test/CodeGen/R600/llvm.AMDGPU.floor.ll.check
new file mode 100644
index 0000000000000000000000000000000000000000..324c10d94c8071d318bf6ad7fca5f7433bf040eb
GIT binary patch
literal 48
ScmZQzAObKlh%hih)Bykh_5c?E

literal 0
HcmV?d00001

diff --git a/test/CodeGen/R600/llvm.AMDGPU.mul.ll b/test/CodeGen/R600/llvm.AMDGPU.mul.ll
new file mode 100644
index 00000000000..3c995c924f8
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.mul.ll
@@ -0,0 +1,16 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = call float @llvm.AMDGPU.mul( float %r0, float %r1)
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.mul(float ,float ) readnone
diff --git a/test/CodeGen/R600/llvm.AMDGPU.mul.ll.check b/test/CodeGen/R600/llvm.AMDGPU.mul.ll.check
new file mode 100644
index 0000000000000000000000000000000000000000..0a79cbaf26320823281d7994304baa7cf0884ea9
GIT binary patch
literal 48
UcmZQzKn9G+90Z$@0R+JS003<O1poj5

literal 0
HcmV?d00001

diff --git a/test/CodeGen/R600/llvm.AMDGPU.pow.ll b/test/CodeGen/R600/llvm.AMDGPU.pow.ll
new file mode 100644
index 00000000000..b692081c13e
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.pow.ll
@@ -0,0 +1,16 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = call float @llvm.AMDGPU.pow( float %r0, float %r1)
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.pow(float ,float ) readnone
diff --git a/test/CodeGen/R600/llvm.AMDGPU.pow.ll.check b/test/CodeGen/R600/llvm.AMDGPU.pow.ll.check
new file mode 100644
index 0000000000000000000000000000000000000000..94af645419bc4b91c600cd3ccec1becf3e680710
GIT binary patch
literal 144
jcmZQzAObKlG&3;5)gf4LAv6XfP&Hvy2u+L(jWG29Jiq}B

literal 0
HcmV?d00001

diff --git a/test/CodeGen/R600/llvm.AMDGPU.rcp.ll b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll
new file mode 100644
index 00000000000..3efae497416
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.AMDGPU.rcp( float %r0)
+   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.rcp(float ) readnone
diff --git a/test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check
new file mode 100644
index 0000000000000000000000000000000000000000..75fe90c5189f26b1fc70e11e050fda17fec9af2a
GIT binary patch
literal 48
ScmZQzAObKlv@tM3)Bykl_yCCj

literal 0
HcmV?d00001

diff --git a/test/CodeGen/R600/llvm.AMDGPU.sin.ll b/test/CodeGen/R600/llvm.AMDGPU.sin.ll
new file mode 100644
index 00000000000..6a427b5d1af
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.sin.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.AMDGPU.sin( float %r0)
+   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.sin(float ) readnone
diff --git a/test/CodeGen/R600/llvm.AMDGPU.sin.ll.check b/test/CodeGen/R600/llvm.AMDGPU.sin.ll.check
new file mode 100644
index 0000000000000000000000000000000000000000..53535543a9413052b39cd74563c225910691dbb4
GIT binary patch
literal 144
scmZSh%K!$=Kb7ntEDVy7fssKHh+zQ1f{CEhARUBNA#^b^^up8w0Get8i2wiq

literal 0
HcmV?d00001

diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
new file mode 100644
index 00000000000..fcabcac89f7
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.AMDGPU.trunc( float %r0)
+   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDGPU.trunc(float ) readnone
diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check
new file mode 100644
index 0000000000000000000000000000000000000000..f9c93b3def54a69e36ab3da1c6f752df053bc7c4
GIT binary patch
literal 48
ScmZQzAObKl2r@82)Bykh+W-^*

literal 0
HcmV?d00001

diff --git a/test/CodeGen/R600/llvm.AMDIL.fabs..ll b/test/CodeGen/R600/llvm.AMDIL.fabs..ll
new file mode 100644
index 00000000000..11430369e4c
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDIL.fabs..ll
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.AMDIL.fabs.( float %r0)
+   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDIL.fabs.(float ) readnone
diff --git a/test/CodeGen/R600/llvm.AMDIL.fabs..ll.check b/test/CodeGen/R600/llvm.AMDIL.fabs..ll.check
new file mode 100644
index 0000000000000000000000000000000000000000..ff3124ca903eda51d51fcb410aec13155eb2920c
GIT binary patch
literal 48
UcmZQz00Kr3fd?=$NW#<r00B+_9RL6T

literal 0
HcmV?d00001

diff --git a/test/CodeGen/R600/llvm.AMDIL.max..ll b/test/CodeGen/R600/llvm.AMDIL.max..ll
new file mode 100644
index 00000000000..337371234ae
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDIL.max..ll
@@ -0,0 +1,16 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = call float @llvm.AMDIL.max.( float %r0, float %r1)
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDIL.max.(float ,float ) readnone
diff --git a/test/CodeGen/R600/llvm.AMDIL.max..ll.check b/test/CodeGen/R600/llvm.AMDIL.max..ll.check
new file mode 100644
index 0000000000000000000000000000000000000000..9ae4070fdc844ce443acffb84b7a1c17367d9bcd
GIT binary patch
literal 48
VcmZQzKn9G+90Z$@ftdj+1pokl00#g7

literal 0
HcmV?d00001

diff --git a/test/CodeGen/R600/llvm.AMDIL.min..ll b/test/CodeGen/R600/llvm.AMDIL.min..ll
new file mode 100644
index 00000000000..76a87188808
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDIL.min..ll
@@ -0,0 +1,16 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check -
+
+
+define void @test() {
+   %r0 = call float @llvm.R600.load.input(i32 0)
+   %r1 = call float @llvm.R600.load.input(i32 1)
+   %r2 = call float @llvm.AMDIL.min.( float %r0, float %r1)
+   call void @llvm.AMDGPU.store.output(float %r2, i32 0)
+   ret void
+}
+
+declare float @llvm.R600.load.input(i32) readnone
+
+declare void @llvm.AMDGPU.store.output(float, i32)
+
+declare float @llvm.AMDIL.min.(float ,float ) readnone
diff --git a/test/CodeGen/R600/llvm.AMDIL.min..ll.check b/test/CodeGen/R600/llvm.AMDIL.min..ll.check
new file mode 100644
index 0000000000000000000000000000000000000000..3d343bdea614fa889e1f636d7fd0401e71ddbf21
GIT binary patch
literal 48
VcmZQzKn9G+90Z$@frSAo1poku00;m8

literal 0
HcmV?d00001

-- 
2.34.1