From 201683b0b76643e9b772b41615bcafa3beb0f0a6 Mon Sep 17 00:00:00 2001
From: qjb <qjb@rock-chips.com>
Date: Tue, 4 Mar 2014 14:10:02 +0800
Subject: [PATCH] rk3288 dts i2s :add i2s,rk610 ctrl,rk610 codec into dts

---
 arch/arm/boot/dts/rk3288-fpga.dts | 69 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/rk3288.dtsi     | 30 ++++++++++++++
 2 files changed, 99 insertions(+)
 mode change 100644 => 100755 arch/arm/boot/dts/rk3288-fpga.dts

diff --git a/arch/arm/boot/dts/rk3288-fpga.dts b/arch/arm/boot/dts/rk3288-fpga.dts
old mode 100644
new mode 100755
index ca4a3b89fa46..6753ec8f3016
--- a/arch/arm/boot/dts/rk3288-fpga.dts
+++ b/arch/arm/boot/dts/rk3288-fpga.dts
@@ -17,4 +17,73 @@
 	fiq-debugger {
 		status = "okay";
 	};
+
+	rockchip-rt5631 {
+		compatible = "rockchip-rt5631";
+		dais {
+			dai0 {
+				codec-name = "rt5631.0-001a";
+				cpu-dai-name = "rockchip-i2s.0";
+				format = "i2s";
+				//continuous-clock;
+				//bitclock-inversion;
+				//frame-inversion;
+				//bitclock-master;
+				//frame-master;
+			};
+		};
+	};
+
+	rockchip-rk610 {
+		compatible = "rockchip-rk610";
+		dais {
+			dai0 {
+				codec-name = "rk610_codec.0-0060";
+				cpu-dai-name = "rockchip-i2s.0";
+				format = "i2s";
+				//continuous-clock;
+				//bitclock-inversion;
+				//frame-inversion;
+				//bitclock-master;
+				//frame-master;
+			};
+		};
+	};
+
+	codec-hdmi-spdif {
+		compatible = "hdmi-spdif";
+	};
+
+	codec-hdmi-i2s {
+		compatible = "hdmi-i2s";
+	};
+
+	codec-hdmi-spdif {
+		compatible = "hdmi-spdif";
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	rt5631@1a {
+		compatible = "rt5631";
+		reg = <0x1a>;
+	};
+
+	rk610ctl@40 {
+		compatible = "rk610_ctl";
+		reg = <0x40>;
+		rk610-reset-io = <&gpio3 GPIO_B2 GPIO_ACTIVE_HIGH>;
+	//	clocks = <&clk_i2s>;
+	//	clock-names = "i2s_clk";
+	};
+
+	rk610codec@60 {//RK610_CODEC addr  from 0x60 to 0x80 (0x60~0x80)
+		compatible = "rk610_codec";
+		reg = <0x60>;
+		spk_ctl_io = <&gpio2 GPIO_D7 GPIO_ACTIVE_HIGH>;
+		boot_depop = <1>;
+		pa_enable_time = <1000>;
+	};
+
 };
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index e8ca9e5957e5..8ec0495e4f5e 100755
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -190,4 +190,34 @@
     clock-names = "hclk_rga", "aclk_rga"; 
 		status = "disabled";
         };
+
+	i2s: rockchip-i2s@0xff890000 {
+		compatible = "rockchip-i2s";
+		reg = <0xff890000 0x10000>;
+		i2s-id = <0>;
+		clocks = <&clk_i2s>;
+		clock-names = "i2s_clk","i2s_mclk";
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+		dmas = <&pdma0 0>,
+			<&pdma0 1>;
+		//#dma-cells = <2>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo0 &i2s0_sdo1 &i2s0_sdo2 &i2s0_sdo3>;
+		pinctrl-1 = <&i2s0_gpio>;
+	};
+
+	spdif: rockchip-spdif@0xff8b0000 {
+		compatible = "rockchip-spdif";
+		reg = <0xff8b0000 0x10000>;	//8channel
+		//reg = <ff880000 0x2000>;//2channel
+		clocks = <&clk_spdif>;
+		clock-names = "spdif_mclk";
+		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+		dmas = <&pdma0 8>;
+		//#dma-cells = <1>;
+		dma-names = "tx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&spdif_tx>;
+	};
 };
-- 
2.34.1