From 20fc6ac99ee24a6901b71a5464c73affb31d2db5 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Tue, 31 Mar 2015 20:35:26 +0000 Subject: [PATCH] [SDAG] Handle non-integer preferred memset types for non-constant values The existing code in getMemsetValue only handled integer-preferred types when the fill value was not a constant. Make this more robust in two ways: 1. If the preferred type is a floating-point value, do the mul-splat trick on the corresponding integer type and then bitcast. 2. If the preferred type is a vector, do the mul-splat trick on one vector element, and then build a vector out of them. Fixes PR22754 (although, we should also turn off use of vector types at -O0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233749 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 19 +++++++++-- test/CodeGen/PowerPC/memset-nc-le.ll | 24 ++++++++++++++ test/CodeGen/PowerPC/memset-nc.ll | 39 +++++++++++++++++++++++ 3 files changed, 80 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/PowerPC/memset-nc-le.ll create mode 100644 test/CodeGen/PowerPC/memset-nc.ll diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index fba750a68d6..c90c27abb3d 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3791,12 +3791,27 @@ static SDValue getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG, return DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(VT), Val), VT); } - Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); + assert(Value.getValueType() == MVT::i8 && "memset with non-byte fill value?"); + EVT IntVT = VT.getScalarType(); + if (!IntVT.isInteger()) + IntVT = EVT::getIntegerVT(*DAG.getContext(), IntVT.getSizeInBits()); + + Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value); if (NumBits > 8) { // Use a multiplication with 0x010101... to extend the input to the // required length. APInt Magic = APInt::getSplat(NumBits, APInt(8, 0x01)); - Value = DAG.getNode(ISD::MUL, dl, VT, Value, DAG.getConstant(Magic, VT)); + Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, + DAG.getConstant(Magic, IntVT)); + } + + if (VT != Value.getValueType() && !VT.isInteger()) + Value = DAG.getNode(ISD::BITCAST, dl, VT.getScalarType(), Value); + if (VT != Value.getValueType()) { + assert(VT.getVectorElementType() == Value.getValueType() && + "value type should be one vector element here"); + SmallVector BVOps(VT.getVectorNumElements(), Value); + Value = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, BVOps); } return Value; diff --git a/test/CodeGen/PowerPC/memset-nc-le.ll b/test/CodeGen/PowerPC/memset-nc-le.ll new file mode 100644 index 00000000000..af8e9c3fb4f --- /dev/null +++ b/test/CodeGen/PowerPC/memset-nc-le.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le" + +; Function Attrs: nounwind +define void @test_vsx() unnamed_addr #0 align 2 { +entry: + %0 = load i32, i32* undef, align 4 + %1 = trunc i32 %0 to i8 + call void @llvm.memset.p0i8.i64(i8* null, i8 %1, i64 32, i32 1, i1 false) + ret void + +; CHECK-LABEL: @test_vsx +; CHECK: stxvd2x +; CHECK: stxvd2x +; CHECK: blr +} + +; Function Attrs: nounwind +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1 + +attributes #0 = { nounwind "target-cpu"="pwr8" } +attributes #1 = { nounwind } + diff --git a/test/CodeGen/PowerPC/memset-nc.ll b/test/CodeGen/PowerPC/memset-nc.ll new file mode 100644 index 00000000000..46341be1c40 --- /dev/null +++ b/test/CodeGen/PowerPC/memset-nc.ll @@ -0,0 +1,39 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-bgq-linux" + +; Function Attrs: nounwind +define void @test_qpx() unnamed_addr #0 align 2 { +entry: + %0 = load i32, i32* undef, align 4 + %1 = trunc i32 %0 to i8 + call void @llvm.memset.p0i8.i64(i8* null, i8 %1, i64 64, i32 32, i1 false) + ret void + +; CHECK-LABEL: @test_qpx +; CHECK: qvstfdx +; CHECK: qvstfdx +; CHECK: blr +} + +; Function Attrs: nounwind +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1 + +; Function Attrs: nounwind +define void @test_vsx() unnamed_addr #2 align 2 { +entry: + %0 = load i32, i32* undef, align 4 + %1 = trunc i32 %0 to i8 + call void @llvm.memset.p0i8.i64(i8* null, i8 %1, i64 32, i32 1, i1 false) + ret void + +; CHECK-LABEL: @test_vsx +; CHECK: stxvw4x +; CHECK: stxvw4x +; CHECK: blr +} + +attributes #0 = { nounwind "target-cpu"="a2q" } +attributes #1 = { nounwind } +attributes #2 = { nounwind "target-cpu"="pwr7" } + -- 2.34.1