From 216def8ecfb8d2b03520a4fe004d498ad7b8b1c9 Mon Sep 17 00:00:00 2001 From: Nate Begeman Date: Fri, 14 Oct 2005 01:29:07 +0000 Subject: [PATCH] fold sext_in_reg, sext_in_reg where both have the same VT. This was popping up in Fourinarow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23722 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 4997dba4680..879dc5b36f7 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1330,7 +1330,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { } // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && - cast(N0.getOperand(1))->getVT() < EVT) { + cast(N0.getOperand(1))->getVT() <= EVT) { return N0; } // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 -- 2.34.1