From 21b5541814d57d0a31f353948e4e933dbb1af6a4 Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Thu, 12 Feb 2009 23:08:38 +0000 Subject: [PATCH] Eliminate a couple of non-DebugLoc BuildMI variants. Modify callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineInstrBuilder.h | 12 ----- lib/Target/ARM/ARMInstrInfo.cpp | 10 ++-- lib/Target/Alpha/AlphaRegisterInfo.cpp | 7 +-- lib/Target/CellSPU/SPUInstrInfo.cpp | 6 ++- lib/Target/IA64/IA64InstrInfo.cpp | 8 +-- lib/Target/Mips/MipsInstrInfo.cpp | 6 ++- lib/Target/PowerPC/PPCInstrInfo.cpp | 35 +++++++------ lib/Target/Sparc/SparcInstrInfo.cpp | 6 ++- lib/Target/X86/X86InstrInfo.cpp | 7 ++- lib/Target/X86/X86RegisterInfo.cpp | 57 +++++++++++++--------- lib/Target/XCore/XCoreRegisterInfo.cpp | 4 +- 11 files changed, 86 insertions(+), 72 deletions(-) diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h index 54fbe27eec7..2ddf1523f08 100644 --- a/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/include/llvm/CodeGen/MachineInstrBuilder.h @@ -98,11 +98,6 @@ public: /// BuildMI - Builder interface. Specify how to create the initial instruction /// itself. /// -inline MachineInstrBuilder BuildMI(MachineFunction &MF, - const TargetInstrDesc &TID) { - return MachineInstrBuilder(MF.CreateMachineInstr(TID, - DebugLoc::getUnknownLoc())); -} inline MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const TargetInstrDesc &TID) { @@ -112,13 +107,6 @@ inline MachineInstrBuilder BuildMI(MachineFunction &MF, /// BuildMI - This version of the builder sets up the first operand as a /// destination virtual register. /// -inline MachineInstrBuilder BuildMI(MachineFunction &MF, - const TargetInstrDesc &TID, - unsigned DestReg) { - return MachineInstrBuilder(MF.CreateMachineInstr(TID, - DebugLoc::getUnknownLoc())) - .addReg(DestReg, true); -} inline MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const TargetInstrDesc &TID, diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 8578284a35d..891d3a4a7eb 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -555,13 +555,14 @@ void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); unsigned Opc = 0; if (RC == ARM::GPRRegisterClass) { ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) { Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR; MachineInstrBuilder MIB = - BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); NewMIs.push_back(MIB); @@ -576,7 +577,7 @@ void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } MachineInstrBuilder MIB = - BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); + BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); AddDefaultPred(MIB); @@ -614,12 +615,13 @@ void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl &Addr, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); unsigned Opc = 0; if (RC == ARM::GPRRegisterClass) { ARMFunctionInfo *AFI = MF.getInfo(); if (AFI->isThumbFunction()) { Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR; - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); NewMIs.push_back(MIB); @@ -633,7 +635,7 @@ void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, Opc = ARM::FLDS; } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = ARMInstrAddOperand(MIB, Addr[i]); AddDefaultPred(MIB); diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 3523b269cf8..a0b6e09c50a 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -125,11 +125,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineInstr *New; if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) { - New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) .addImm(-Amount).addReg(Alpha::R30); } else { assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP); - New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) .addImm(Amount).addReg(Alpha::R30); } @@ -188,7 +188,8 @@ void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false); MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); //insert the new - MachineInstr* nMI=BuildMI(MF, TII.get(Alpha::LDAH), Alpha::R28) + MachineInstr* nMI=BuildMI(MF, MI.getDebugLoc(), + TII.get(Alpha::LDAH), Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); MBB.insert(II, nMI); } else { diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index 182b3a75170..d2ec7b1a1e4 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -349,7 +349,8 @@ void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)) + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; @@ -431,7 +432,8 @@ void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp index a6e4d97f6e3..b4eb889e70c 100644 --- a/lib/Target/IA64/IA64InstrInfo.cpp +++ b/lib/Target/IA64/IA64InstrInfo.cpp @@ -130,7 +130,8 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, "sorry, I don't know how to store this sort of reg\n"); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) @@ -185,10 +186,11 @@ void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, Opc = IA64::LD1; } else { assert(0 && - "sorry, I don't know how to store this sort of reg\n"); + "sorry, I don't know how to load this sort of reg\n"); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 167aa45632d..ad12e8db9bb 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -225,7 +225,8 @@ void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else assert(0 && "Can't store this register"); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)) + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; @@ -278,7 +279,8 @@ void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, else assert(0 && "Can't load this register"); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 0097393b722..eac15bded57 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -355,43 +355,44 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); if (RC == PPC::GPRCRegisterClass) { if (SrcReg != PPC::LR) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else { // FIXME: this spills LR immediately to memory in one step. To do this, // we use R11, which we know cannot be used in the prolog/epilog. This is // a hack. - NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11)); - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW)) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) .addReg(PPC::R11, false, false, isKill), FrameIdx)); } } else if (RC == PPC::G8RCRegisterClass) { if (SrcReg != PPC::LR8) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else { // FIXME: this spills LR immediately to memory in one step. To do this, // we use R11, which we know cannot be used in the prolog/epilog. This is // a hack. - NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11)); - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD)) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) .addReg(PPC::X11, false, false, isKill), FrameIdx)); } } else if (RC == PPC::F8RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else if (RC == PPC::F4RCRegisterClass) { - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else if (RC == PPC::CRRCRegisterClass) { if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { // FIXME (64-bit): Enable - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) .addReg(SrcReg, false, false, isKill), FrameIdx)); return true; @@ -399,18 +400,18 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, // FIXME: We use R0 here, because it isn't available for RA. We need to // store the CR in the low 4-bits of the saved value. First, issue a MFCR // to save all of the CRBits. - NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0)); + NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), PPC::R0)); // If the saved register wasn't CR0, shift the bits left so that they are // in CR0's slot. if (SrcReg != PPC::CR0) { unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; // rlwinm r0, r0, ShiftBits, 0, 31. - NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0) .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31)); } - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW)) + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) .addReg(PPC::R0, false, false, isKill), FrameIdx)); } @@ -446,9 +447,9 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, // STVX VAL, 0, R0 // // FIXME: We use R0 here, because it isn't available for RA. - NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0), + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), FrameIdx, 0, 0)); - NewMIs.push_back(BuildMI(MF, get(PPC::STVX)) + NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0)); } else { assert(0 && "Unknown regclass!"); @@ -490,6 +491,7 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, return; } + DebugLoc DL = DebugLoc::getUnknownLoc(); unsigned Opc = 0; if (RC == PPC::GPRCRegisterClass) { Opc = PPC::STW; @@ -505,7 +507,7 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)) + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; @@ -644,7 +646,8 @@ void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index cbfde30ba16..9a3ff12bf6a 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -167,6 +167,7 @@ void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const { unsigned Opc = 0; + DebugLoc DL = DebugLoc::getUnknownLoc(); if (RC == SP::IntRegsRegisterClass) Opc = SP::STri; else if (RC == SP::FPRegsRegisterClass) @@ -175,7 +176,7 @@ void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, Opc = SP::STDFri; else assert(0 && "Can't load this register"); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) @@ -222,7 +223,8 @@ void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, Opc = SP::LDDFri; else assert(0 && "Can't load this register"); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 97c0d39dc0b..9408be32dba 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -1850,7 +1850,8 @@ void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isAligned = (RI.getStackAlignment() >= 16) || RI.needsStackRealignment(MF); unsigned Opc = getStoreRegOpcode(RC, isAligned); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = X86InstrAddOperand(MIB, Addr[i]); MIB.addReg(SrcReg, false, false, isKill); @@ -1915,7 +1916,8 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, bool isAligned = (RI.getStackAlignment() >= 16) || RI.needsStackRealignment(MF); unsigned Opc = getLoadRegOpcode(RC, isAligned); - MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); + DebugLoc DL = DebugLoc::getUnknownLoc(); + MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = X86InstrAddOperand(MIB, Addr[i]); NewMIs.push_back(MIB); @@ -2287,6 +2289,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); if (I == MemOp2RegOpTable.end()) return false; + DebugLoc dl = MI->getDebugLoc(); unsigned Opc = I->second.first; unsigned Index = I->second.second & 0xf; bool FoldedLoad = I->second.second & (1 << 4); diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 59e49eaf4f9..0130ba2c49d 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -396,7 +396,8 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineInstr *New = 0; if (Old->getOpcode() == getCallFrameSetupOpcode()) { - New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), + New = BuildMI(MF, Old->getDebugLoc(), + TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr).addReg(StackPtr).addImm(Amount); } else { assert(Old->getOpcode() == getCallFrameDestroyOpcode()); @@ -407,7 +408,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, unsigned Opc = (Amount < 128) ? (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri); - New = BuildMI(MF, TII.get(Opc), StackPtr) + New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr) .addReg(StackPtr).addImm(Amount); } } @@ -428,8 +429,10 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, unsigned Opc = (CalleeAmt < 128) ? (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); + MachineInstr *Old = I; MachineInstr *New = - BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt); + BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), + StackPtr).addReg(StackPtr).addImm(CalleeAmt); // The EFLAGS implicit def is dead. New->getOperand(3).setIsDead(); @@ -723,6 +726,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || !Fn->doesNotThrow() || UnwindTablesMandatory; + DebugLoc DL = DebugLoc::getUnknownLoc(); // Prepare for frame info. unsigned FrameLabelId = 0; @@ -757,7 +761,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { // size is bigger than the callers. if (TailCallReturnAddrDelta < 0) { MachineInstr *MI = - BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri), + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri), StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta); // The EFLAGS implicit def is dead. MI->getOperand(3).setIsDead(); @@ -778,18 +782,19 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { MFI->setOffsetAdjustment(-NumBytes); // Save EBP into the appropriate stack slot... - BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) .addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); if (needsFrameMoves) { // Mark effective beginning of when frame pointer becomes valid. FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId); + BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId); } // Update EBP with the new base value... - BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) - .addReg(StackPtr); + BuildMI(MBB, MBBI, DL, + TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) + .addReg(StackPtr); // Mark the FramePtr as live-in in every block except the entry. for (MachineFunction::iterator I = next(MF.begin()), E = MF.end(); @@ -799,7 +804,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { // Realign stack if (needsStackRealignment(MF)) { MachineInstr *MI = - BuildMI(MBB, MBBI, + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr).addReg(StackPtr).addImm(-MaxAlign); // The EFLAGS implicit def is dead. @@ -812,7 +817,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { if (needsFrameMoves) { // Mark effective beginning of when frame pointer is ready. ReadyLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId); + BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId); } // Skip the callee-saved push instructions. @@ -838,20 +843,22 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { // necessary to ensure that the guard pages used by the OS virtual memory // manager are allocated in correct sequence. if (!isEAXAlive) { - BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes); - BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)) + BuildMI(MBB, MBBI,DL, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes); + BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32)) .addExternalSymbol("_alloca"); } else { // Save EAX - BuildMI(MBB, MBBI, TII.get(X86::PUSH32r)) + BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r)) .addReg(X86::EAX, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); // Allocate NumBytes-4 bytes on stack. We'll also use 4 already // allocated bytes for EAX. - BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4); - BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)) + BuildMI(MBB, MBBI, DL, + TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4); + BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32)) .addExternalSymbol("_alloca"); // Restore EAX - MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX), + MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), + X86::EAX), StackPtr, false, NumBytes-4); MBB.insert(MBBI, MI); } @@ -879,6 +886,7 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, X86MachineFunctionInfo *X86FI = MF.getInfo(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); unsigned RetOpcode = MBBI->getOpcode(); + DebugLoc DL = DebugLoc::getUnknownLoc(); switch (RetOpcode) { case X86::RET: @@ -911,7 +919,8 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, NumBytes = FrameSize - CSSize; // pop EBP. - BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); + BuildMI(MBB, MBBI, DL, + TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); } else NumBytes = StackSize - CSSize; @@ -942,17 +951,17 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, MBBI = prior(LastCSPop); } - BuildMI(MBB, MBBI, + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr).addReg(FramePtr); } else if (MFI->hasVarSizedObjects()) { if (CSSize) { unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r; - MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr), + MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr), FramePtr, false, -CSSize); MBB.insert(MBBI, MI); } else - BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr).addReg(FramePtr); } else { @@ -966,7 +975,7 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, MBBI = prior(MBB.end()); MachineOperand &DestAddr = MBBI->getOperand(0); assert(DestAddr.isReg() && "Offset should be in register!"); - BuildMI(MBB, MBBI, + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr).addReg(DestAddr.getReg()); // Tail call return: adjust the stack pointer and jump to callee @@ -992,12 +1001,12 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, } // Jump to label or value in register. if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64) - BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)). + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)). addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); else if (RetOpcode== X86::TCRETURNri64) { - BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg()); + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg()); } else - BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg()); + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg()); // Delete the pseudo instruction TCRETURN. MBB.erase(MBBI); } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) && diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index d93dad83a8c..b194b5e46e7 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -150,12 +150,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineInstr *New; if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) { int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; - New=BuildMI(MF, TII.get(Opcode)) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode)) .addImm(Amount); } else { assert(Old->getOpcode() == XCore::ADJCALLSTACKUP); int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; - New=BuildMI(MF, TII.get(Opcode), XCore::SP) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP) .addImm(Amount); } -- 2.34.1