From 21f587ca243c2265e9b8aa81481f9085cd0e7b68 Mon Sep 17 00:00:00 2001
From: Jim Laskey <jlaskey@mac.com>
Date: Tue, 18 Oct 2005 16:59:23 +0000
Subject: [PATCH] Simple edits; remove unimplimented cases and clarify long
 haul SLU cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23788 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/PowerPC/PPCScheduleG3.td     | 26 -------------------------
 lib/Target/PowerPC/PPCScheduleG4.td     | 15 --------------
 lib/Target/PowerPC/PPCScheduleG4Plus.td | 12 ------------
 lib/Target/PowerPC/PPCScheduleG5.td     | 11 +++--------
 4 files changed, 3 insertions(+), 61 deletions(-)

diff --git a/lib/Target/PowerPC/PPCScheduleG3.td b/lib/Target/PowerPC/PPCScheduleG3.td
index 431c7948599..3931e2084b6 100644
--- a/lib/Target/PowerPC/PPCScheduleG3.td
+++ b/lib/Target/PowerPC/PPCScheduleG3.td
@@ -15,21 +15,14 @@
 def G3Itineraries : ProcessorItineraries<G3, [
   InstrItinData<IntGeneral  , [InstrStage<1, [IU1, IU2]>]>,
   InstrItinData<IntCompare  , [InstrStage<1, [IU1, IU2]>]>,
-  InstrItinData<IntDivD     , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntDivW     , [InstrStage<19, [IU1]>]>,
   InstrItinData<IntMFFS     , [InstrStage<1, [FPU1]>]>,
-  InstrItinData<IntMFVSCR   , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntMTFSB0   , [InstrStage<3, [FPU1]>]>,
-  InstrItinData<IntMTSRD    , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<IntMulHD    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntMulHW    , [InstrStage<5, [IU1]>]>,
   InstrItinData<IntMulHWU   , [InstrStage<6, [IU1]>]>,
   InstrItinData<IntMulLI    , [InstrStage<3, [IU1]>]>,
-  InstrItinData<IntRFID     , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<IntRotateD  , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntRotate   , [InstrStage<1, [IU1, IU2]>]>,
   InstrItinData<IntShift    , [InstrStage<1, [IU1, IU2]>]>,
-  InstrItinData<IntTrapD    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntTrapW    , [InstrStage<2, [IU1, IU2]>]>,
   InstrItinData<BrB         , [InstrStage<1, [BPU]>]>,
   InstrItinData<BrCR        , [InstrStage<1, [SRU]>]>,
@@ -39,23 +32,13 @@ def G3Itineraries : ProcessorItineraries<G3, [
   InstrItinData<LdStDCBF    , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStDCBI    , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStDCBT    , [InstrStage<2, [SLU]>]>,
-  InstrItinData<LdStDSS     , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStICBI    , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStLBZUX   , [InstrStage<2, [SLU]>]>,
-  InstrItinData<LdStLD      , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<LdStLDARX   , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStLFD     , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStLFDU    , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStLHA     , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStLMW     , [InstrStage<34, [SLU]>]>,
-  InstrItinData<LdStLVEBX   , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<LdStLWA     , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStLWARX   , [InstrStage<3, [SLU]>]>,
-  InstrItinData<LdStSLBIA   , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<LdStSLBIE   , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<LdStSTD     , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<LdStSTDCX   , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<LdStSTVEBX  , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStSTWCX   , [InstrStage<8, [SLU]>]>,
   InstrItinData<LdStSync    , [InstrStage<3, [SLU]>]>,
   InstrItinData<SprISYNC    , [InstrStage<2, [SRU]>]>,
@@ -77,13 +60,4 @@ def G3Itineraries : ProcessorItineraries<G3, [
   InstrItinData<FPDivS      , [InstrStage<17, [FPU1]>]>,
   InstrItinData<FPFused     , [InstrStage<2, [FPU1]>]>,
   InstrItinData<FPRes       , [InstrStage<10, [FPU1]>]>,
-  InstrItinData<FPSqrt      , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<VecGeneral  , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<VecFP       , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<VecFPCompare, [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<VecComplex  , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<VecPerm     , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<VecFPRound  , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<VecVSL      , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<VecVSR      , [InstrStage<0, [NoUnit]>]>
 ]>;
diff --git a/lib/Target/PowerPC/PPCScheduleG4.td b/lib/Target/PowerPC/PPCScheduleG4.td
index 28fb004f625..6984ae9b0a6 100644
--- a/lib/Target/PowerPC/PPCScheduleG4.td
+++ b/lib/Target/PowerPC/PPCScheduleG4.td
@@ -14,46 +14,32 @@
 def G4Itineraries : ProcessorItineraries<G4, [
   InstrItinData<IntGeneral  , [InstrStage<1, [IU1, IU2]>]>,
   InstrItinData<IntCompare  , [InstrStage<1, [IU1, IU2]>]>,
-  InstrItinData<IntDivD     , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntDivW     , [InstrStage<19, [IU1]>]>,
   InstrItinData<IntMFFS     , [InstrStage<3, [FPU1]>]>,
   InstrItinData<IntMFVSCR   , [InstrStage<1, [VIU1]>]>,
   InstrItinData<IntMTFSB0   , [InstrStage<3, [FPU1]>]>,
-  InstrItinData<IntMTSRD    , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<IntMulHD    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntMulHW    , [InstrStage<5, [IU1]>]>,
   InstrItinData<IntMulHWU   , [InstrStage<6, [IU1]>]>,
   InstrItinData<IntMulLI    , [InstrStage<3, [IU1]>]>,
-  InstrItinData<IntRFID     , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<IntRotateD  , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntRotate   , [InstrStage<1, [IU1, IU2]>]>,
   InstrItinData<IntShift    , [InstrStage<1, [IU1, IU2]>]>,
-  InstrItinData<IntTrapD    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntTrapW    , [InstrStage<2, [IU1, IU2]>]>,
   InstrItinData<BrB         , [InstrStage<1, [BPU]>]>,
   InstrItinData<BrCR        , [InstrStage<1, [SRU]>]>,
   InstrItinData<BrMCR       , [InstrStage<1, [SRU]>]>,
   InstrItinData<BrMCRX      , [InstrStage<1, [SRU]>]>,
-  InstrItinData<LdStDCBA    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStDCBF    , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStDCBI    , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStDCBT    , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStDSS     , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStICBI    , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStLBZUX   , [InstrStage<2, [SLU]>]>,
-  InstrItinData<LdStLD      , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<LdStLDARX   , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStLFD     , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStLFDU    , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStLHA     , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStLMW     , [InstrStage<34, [SLU]>]>,
   InstrItinData<LdStLVEBX   , [InstrStage<2, [SLU]>]>,
-  InstrItinData<LdStLWA     , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStLWARX   , [InstrStage<3, [SLU]>]>,
-  InstrItinData<LdStSLBIA   , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<LdStSLBIE   , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<LdStSTD     , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<LdStSTDCX   , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStSTVEBX  , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStSTWCX   , [InstrStage<5, [SLU]>]>,
   InstrItinData<LdStSync    , [InstrStage<8, [SLU]>]>,
@@ -76,7 +62,6 @@ def G4Itineraries : ProcessorItineraries<G4, [
   InstrItinData<FPDivS      , [InstrStage<17, [FPU1]>]>,
   InstrItinData<FPFused     , [InstrStage<1, [FPU1]>]>,
   InstrItinData<FPRes       , [InstrStage<10, [FPU1]>]>,
-  InstrItinData<FPSqrt      , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<VecGeneral  , [InstrStage<1, [VIU1]>]>,
   InstrItinData<VecFP       , [InstrStage<4, [VFPU]>]>,
   InstrItinData<VecFPCompare, [InstrStage<1, [VIU1]>]>,
diff --git a/lib/Target/PowerPC/PPCScheduleG4Plus.td b/lib/Target/PowerPC/PPCScheduleG4Plus.td
index b1ec17e7807..7d028c2c657 100644
--- a/lib/Target/PowerPC/PPCScheduleG4Plus.td
+++ b/lib/Target/PowerPC/PPCScheduleG4Plus.td
@@ -14,35 +14,26 @@
 def G4PlusItineraries : ProcessorItineraries<G4Plus, [
   InstrItinData<IntGeneral  , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
   InstrItinData<IntCompare  , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
-  InstrItinData<IntDivD     , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntDivW     , [InstrStage<23, [IU2]>]>,
   InstrItinData<IntMFFS     , [InstrStage<5, [FPU1]>]>,
   InstrItinData<IntMFVSCR   , [InstrStage<2, [VFPU]>]>,
   InstrItinData<IntMTFSB0   , [InstrStage<5, [FPU1]>]>,
-  InstrItinData<IntMTSRD    , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<IntMulHD    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntMulHW    , [InstrStage<4, [IU2]>]>,
   InstrItinData<IntMulHWU   , [InstrStage<4, [IU2]>]>,
   InstrItinData<IntMulLI    , [InstrStage<3, [IU2]>]>,
-  InstrItinData<IntRFID     , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<IntRotateD  , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntRotate   , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
   InstrItinData<IntShift    , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
-  InstrItinData<IntTrapD    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntTrapW    , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
   InstrItinData<BrB         , [InstrStage<1, [BPU]>]>,
   InstrItinData<BrCR        , [InstrStage<2, [IU2]>]>,
   InstrItinData<BrMCR       , [InstrStage<2, [IU2]>]>,
   InstrItinData<BrMCRX      , [InstrStage<2, [IU2]>]>,
-  InstrItinData<LdStDCBA    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStDCBF    , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStDCBI    , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStDCBT    , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStDSS     , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStICBI    , [InstrStage<3, [IU2]>]>,
   InstrItinData<LdStLBZUX   , [InstrStage<3, [SLU]>]>,
-  InstrItinData<LdStLD      , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<LdStLDARX   , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStLFD     , [InstrStage<4, [SLU]>]>,
   InstrItinData<LdStLFDU    , [InstrStage<4, [SLU]>]>,
   InstrItinData<LdStLHA     , [InstrStage<3, [SLU]>]>,
@@ -50,8 +41,6 @@ def G4PlusItineraries : ProcessorItineraries<G4Plus, [
   InstrItinData<LdStLVEBX   , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStLWA     , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStLWARX   , [InstrStage<3, [SLU]>]>,
-  InstrItinData<LdStSLBIA   , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<LdStSLBIE   , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStSTD     , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStSTDCX   , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStSTVEBX  , [InstrStage<3, [SLU]>]>,
@@ -76,7 +65,6 @@ def G4PlusItineraries : ProcessorItineraries<G4Plus, [
   InstrItinData<FPDivS      , [InstrStage<21, [FPU1]>]>,
   InstrItinData<FPFused     , [InstrStage<5, [FPU1]>]>,
   InstrItinData<FPRes       , [InstrStage<14, [FPU1]>]>,
-  InstrItinData<FPSqrt      , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<VecGeneral  , [InstrStage<1, [VIU1]>]>,
   InstrItinData<VecFP       , [InstrStage<4, [VFPU]>]>,
   InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,
diff --git a/lib/Target/PowerPC/PPCScheduleG5.td b/lib/Target/PowerPC/PPCScheduleG5.td
index 33fe71d62a6..4738b892992 100644
--- a/lib/Target/PowerPC/PPCScheduleG5.td
+++ b/lib/Target/PowerPC/PPCScheduleG5.td
@@ -19,7 +19,6 @@ def G5Itineraries : ProcessorItineraries<G5, [
   InstrItinData<IntMFFS     , [InstrStage<6, [IU2]>]>,
   InstrItinData<IntMFVSCR   , [InstrStage<1, [VFPU]>]>,
   InstrItinData<IntMTFSB0   , [InstrStage<6, [FPU1, FPU2]>]>,
-  InstrItinData<IntMTSRD    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<IntMulHD    , [InstrStage<7, [IU1, IU2]>]>,
   InstrItinData<IntMulHW    , [InstrStage<5, [IU1, IU2]>]>,
   InstrItinData<IntMulHWU   , [InstrStage<5, [IU1, IU2]>]>,
@@ -34,12 +33,10 @@ def G5Itineraries : ProcessorItineraries<G5, [
   InstrItinData<BrCR        , [InstrStage<4, [BPU]>]>,
   InstrItinData<BrMCR       , [InstrStage<2, [BPU]>]>,
   InstrItinData<BrMCRX      , [InstrStage<3, [BPU]>]>,
-  InstrItinData<LdStDCBA    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStDCBF    , [InstrStage<3, [SLU]>]>,
-  InstrItinData<LdStDCBI    , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<LdStDCBT    , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStDSS     , [InstrStage<10, [SLU]>]>,
-  InstrItinData<LdStICBI    , [InstrStage<0, [SLU]>]>,
+  InstrItinData<LdStICBI    , [InstrStage<40, [SLU]>]>,
   InstrItinData<LdStLBZUX   , [InstrStage<4, [SLU]>]>,
   InstrItinData<LdStLD      , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStLDARX   , [InstrStage<11, [SLU]>]>,
@@ -50,14 +47,14 @@ def G5Itineraries : ProcessorItineraries<G5, [
   InstrItinData<LdStLVEBX   , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStLWA     , [InstrStage<5, [SLU]>]>,
   InstrItinData<LdStLWARX   , [InstrStage<11, [SLU]>]>,
-  InstrItinData<LdStSLBIA   , [InstrStage<0, [SLU]>]>,
+  InstrItinData<LdStSLBIA   , [InstrStage<40, [SLU]>]>, // needs work
   InstrItinData<LdStSLBIE   , [InstrStage<2, [SLU]>]>,
   InstrItinData<LdStSTD     , [InstrStage<3, [SLU]>]>,
   InstrItinData<LdStSTDCX   , [InstrStage<11, [SLU]>]>,
   InstrItinData<LdStSTVEBX  , [InstrStage<5, [SLU]>]>,
   InstrItinData<LdStSTWCX   , [InstrStage<11, [SLU]>]>,
   InstrItinData<LdStSync    , [InstrStage<35, [SLU]>]>,
-  InstrItinData<SprISYNC    , [InstrStage<0, [SLU]>]>,
+  InstrItinData<SprISYNC    , [InstrStage<40, [SLU]>]>, // needs work
   InstrItinData<SprMFSR     , [InstrStage<3, [SLU]>]>,
   InstrItinData<SprMTMSR    , [InstrStage<3, [SLU]>]>,
   InstrItinData<SprMTSR     , [InstrStage<3, [SLU]>]>,
@@ -67,8 +64,6 @@ def G5Itineraries : ProcessorItineraries<G5, [
   InstrItinData<SprMFSPR    , [InstrStage<3, [IU2]>]>,
   InstrItinData<SprMFTB     , [InstrStage<10, [IU2]>]>,
   InstrItinData<SprMTSPR    , [InstrStage<8, [IU2]>]>,
-  InstrItinData<SprMTSRIN   , [InstrStage<0, [NoUnit]>]>,
-  InstrItinData<SprRFI      , [InstrStage<0, [NoUnit]>]>,
   InstrItinData<SprSC       , [InstrStage<1, [IU2]>]>,
   InstrItinData<FPGeneral   , [InstrStage<6, [FPU1, FPU2]>]>,
   InstrItinData<FPCompare   , [InstrStage<8, [FPU1, FPU2]>]>,
-- 
2.34.1