From 22bab315d1f002334ebbc1dc3998c5d13ef42ab8 Mon Sep 17 00:00:00 2001 From: dkl Date: Tue, 24 Jun 2014 18:00:38 +0800 Subject: [PATCH] clk: rk3288: modify RK3288_LIMIT_PLL_VIO0/1 This commit corresponds to commit debf1d2237185a26503d737d54db730f62cf5ea5. --- drivers/clk/rockchip/clk-ops.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c index 3417e27769b0..7107134a8e7e 100644 --- a/drivers/clk/rockchip/clk-ops.c +++ b/drivers/clk/rockchip/clk-ops.c @@ -558,7 +558,7 @@ const struct clk_ops clkops_rate_3288_usb480m = { .recalc_rate = clk_3288_usb480m_recalc_rate, }; -#define RK3288_LIMIT_PLL_VIO0 (400*MHZ) +#define RK3288_LIMIT_PLL_VIO0 (410*MHZ) static long clk_3288_dclk_lcdc0_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, @@ -619,7 +619,7 @@ const struct clk_ops clkops_rate_3288_dclk_lcdc0 = { .recalc_rate = clk_divider_recalc_rate, }; -#define RK3288_LIMIT_PLL_VIO1 (410*MHZ) +#define RK3288_LIMIT_PLL_VIO1 (350*MHZ) static long clk_3288_dclk_lcdc1_determine_rate(struct clk_hw *hw, unsigned long rate, unsigned long *best_parent_rate, -- 2.34.1