From 23ed37a6b76e79272194fb46597f7280661b828f Mon Sep 17 00:00:00 2001 From: Ahmed Bougacha Date: Fri, 31 May 2013 23:45:26 +0000 Subject: [PATCH] Make SubRegIndex size mandatory, following r183020. This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/MC/MCRegisterInfo.h | 15 +++++++++------ include/llvm/Target/Target.td | 9 +++++++-- lib/MC/MCRegisterInfo.cpp | 17 ++++++++--------- lib/Target/AArch64/AArch64RegisterInfo.td | 12 ++++++------ lib/Target/Hexagon/HexagonRegisterInfo.td | 4 ++-- lib/Target/MSP430/MSP430RegisterInfo.td | 2 +- lib/Target/Mips/MipsRegisterInfo.td | 20 ++++++++++---------- lib/Target/PowerPC/PPCRegisterInfo.td | 10 +++++----- lib/Target/R600/AMDGPURegisterInfo.td | 3 ++- lib/Target/Sparc/SparcRegisterInfo.td | 4 ++-- lib/Target/SystemZ/SystemZRegisterInfo.td | 7 ++++--- utils/TableGen/CodeGenRegisters.cpp | 15 ++++++++++++++- utils/TableGen/CodeGenRegisters.h | 6 ++---- utils/TableGen/RegisterInfoEmitter.cpp | 4 ++-- 14 files changed, 74 insertions(+), 54 deletions(-) diff --git a/include/llvm/MC/MCRegisterInfo.h b/include/llvm/MC/MCRegisterInfo.h index 002f71d5018..3fa89c109c1 100644 --- a/include/llvm/MC/MCRegisterInfo.h +++ b/include/llvm/MC/MCRegisterInfo.h @@ -338,12 +338,15 @@ public: /// otherwise. unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const; - /// \brief Get the bit range covered by a given sub-register index. - /// In some cases, for instance non-contiguous synthesized indices, - /// there is no meaningful bit range to get, so return true if \p Offset - /// and \p Size were set. - bool getSubRegIdxCoveredBits(unsigned Idx, - unsigned &Offset, unsigned &Size) const; + /// \brief Get the size of the bit range covered by a sub-register index. + /// If the index isn't continuous, return the sum of the sizes of its parts. + /// If the index is used to access subregisters of different sizes, return -1. + unsigned getSubRegIdxSize(unsigned Idx) const; + + /// \brief Get the offset of the bit range covered by a sub-register index. + /// If an Offset doesn't make sense (the index isn't continuous, or is used to + /// access sub-registers at different offsets), return -1. + unsigned getSubRegIdxOffset(unsigned Idx) const; /// \brief Return the human-readable symbolic target-specific name for the /// specified physical register. diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index c201f6baab0..a9644d4dd5e 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -22,13 +22,16 @@ include "llvm/IR/Intrinsics.td" class RegisterClass; // Forward def // SubRegIndex - Use instances of SubRegIndex to identify subregisters. -class SubRegIndex { +class SubRegIndex { string Namespace = ""; // Size - Size (in bits) of the sub-registers represented by this index. int Size = size; // Offset - Offset of the first bit that is part of this sub-register index. + // Set it to -1 if the same index is used to represent sub-registers that can + // be at different offsets (for example when using an index to access an + // element in a register tuple). int Offset = offset; // ComposedOf - A list of two SubRegIndex instances, [A, B]. @@ -58,7 +61,9 @@ class SubRegIndex { // ComposedSubRegIndex - A sub-register that is the result of composing A and B. // Offset is set to the sum of A and B's Offsets. Size is set to B's Size. class ComposedSubRegIndex - : SubRegIndex { + : SubRegIndex { // See SubRegIndex. let ComposedOf = [A, B]; } diff --git a/lib/MC/MCRegisterInfo.cpp b/lib/MC/MCRegisterInfo.cpp index 06d6d9680dd..ce79cd5c2c6 100644 --- a/lib/MC/MCRegisterInfo.cpp +++ b/lib/MC/MCRegisterInfo.cpp @@ -46,17 +46,16 @@ unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { return 0; } -bool MCRegisterInfo::getSubRegIdxCoveredBits(unsigned Idx, unsigned &Offset, - unsigned &Size) const { +unsigned MCRegisterInfo::getSubRegIdxSize(unsigned Idx) const { assert(Idx && Idx < getNumSubRegIndices() && "This is not a subregister index"); - // Get a pointer to the corresponding SubRegIdxRanges struct. - const SubRegCoveredBits *Bits = &SubRegIdxRanges[Idx]; - if (Bits->Offset == (uint16_t)-1 || Bits->Size == (uint16_t)-1) - return false; - Offset = Bits->Offset; - Size = Bits->Size; - return true; + return SubRegIdxRanges[Idx].Size; +} + +unsigned MCRegisterInfo::getSubRegIdxOffset(unsigned Idx) const { + assert(Idx && Idx < getNumSubRegIndices() && + "This is not a subregister index"); + return SubRegIdxRanges[Idx].Offset; } int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { diff --git a/lib/Target/AArch64/AArch64RegisterInfo.td b/lib/Target/AArch64/AArch64RegisterInfo.td index bd79546371c..cc2bb6135cc 100644 --- a/lib/Target/AArch64/AArch64RegisterInfo.td +++ b/lib/Target/AArch64/AArch64RegisterInfo.td @@ -12,15 +12,15 @@ //===----------------------------------------------------------------------===// let Namespace = "AArch64" in { -def sub_128 : SubRegIndex; -def sub_64 : SubRegIndex; -def sub_32 : SubRegIndex; -def sub_16 : SubRegIndex; -def sub_8 : SubRegIndex; +def sub_128 : SubRegIndex<128>; +def sub_64 : SubRegIndex<64>; +def sub_32 : SubRegIndex<32>; +def sub_16 : SubRegIndex<16>; +def sub_8 : SubRegIndex<8>; // The VPR registers are handled as sub-registers of FPR equivalents, but // they're really the same thing. We give this concept a special index. -def sub_alias : SubRegIndex; +def sub_alias : SubRegIndex<128>; } // Registers are identified with 5-bit ID numbers. diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.td b/lib/Target/Hexagon/HexagonRegisterInfo.td index fe41fc3bc60..8ea1b7e75db 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -57,8 +57,8 @@ let Namespace = "Hexagon" in { let Aliases = [R]; } - def subreg_loreg : SubRegIndex; - def subreg_hireg : SubRegIndex; + def subreg_loreg : SubRegIndex<32>; + def subreg_hireg : SubRegIndex<32, 32>; // Integer registers. def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>; diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td index 07619d0675b..4010781a860 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.td +++ b/lib/Target/MSP430/MSP430RegisterInfo.td @@ -43,7 +43,7 @@ def R13B : MSP430Reg<13, "r13">; def R14B : MSP430Reg<14, "r14">; def R15B : MSP430Reg<15, "r15">; -def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; } +def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; } let SubRegIndices = [subreg_8bit] in { def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>; diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 229f1677c04..ad6912c557b 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -11,16 +11,16 @@ // Declarations that describe the MIPS register file //===----------------------------------------------------------------------===// let Namespace = "Mips" in { -def sub_fpeven : SubRegIndex; -def sub_fpodd : SubRegIndex; -def sub_32 : SubRegIndex; -def sub_lo : SubRegIndex; -def sub_hi : SubRegIndex; -def sub_dsp16_19 : SubRegIndex; -def sub_dsp20 : SubRegIndex; -def sub_dsp21 : SubRegIndex; -def sub_dsp22 : SubRegIndex; -def sub_dsp23 : SubRegIndex; +def sub_fpeven : SubRegIndex<32>; +def sub_fpodd : SubRegIndex<32, 32>; +def sub_32 : SubRegIndex<32>; +def sub_lo : SubRegIndex<32>; +def sub_hi : SubRegIndex<32, 32>; +def sub_dsp16_19 : SubRegIndex<4, 16>; +def sub_dsp20 : SubRegIndex<1, 20>; +def sub_dsp21 : SubRegIndex<1, 21>; +def sub_dsp22 : SubRegIndex<1, 22>; +def sub_dsp23 : SubRegIndex<1, 23>; } class Unallocatable { diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 57a25f5143f..b1b4f063944 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -11,11 +11,11 @@ //===----------------------------------------------------------------------===// let Namespace = "PPC" in { -def sub_lt : SubRegIndex; -def sub_gt : SubRegIndex; -def sub_eq : SubRegIndex; -def sub_un : SubRegIndex; -def sub_32 : SubRegIndex; +def sub_lt : SubRegIndex<1>; +def sub_gt : SubRegIndex<1, 1>; +def sub_eq : SubRegIndex<1, 2>; +def sub_un : SubRegIndex<1, 3>; +def sub_32 : SubRegIndex<32>; } diff --git a/lib/Target/R600/AMDGPURegisterInfo.td b/lib/Target/R600/AMDGPURegisterInfo.td index b5aca0347fb..835a1464395 100644 --- a/lib/Target/R600/AMDGPURegisterInfo.td +++ b/lib/Target/R600/AMDGPURegisterInfo.td @@ -14,7 +14,8 @@ let Namespace = "AMDGPU" in { foreach Index = 0-15 in { - def sub#Index : SubRegIndex; + // Indices are used in a variety of ways here, so don't set a size/offset. + def sub#Index : SubRegIndex<-1, -1>; } def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">; diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index d1edcb6de1f..b57fd3ddafb 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -21,8 +21,8 @@ class SparcCtrlReg: Register { } let Namespace = "SP" in { -def sub_even : SubRegIndex; -def sub_odd : SubRegIndex; +def sub_even : SubRegIndex<32>; +def sub_odd : SubRegIndex<32, 32>; } // Registers are identified with 5-bit ID numbers. diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td index 7795fffb640..d65553e7500 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.td +++ b/lib/Target/SystemZ/SystemZRegisterInfo.td @@ -21,9 +21,10 @@ class SystemZRegWithSubregs subregs> } let Namespace = "SystemZ" in { -def subreg_32bit : SubRegIndex; // could also be known as "subreg_high32" -def subreg_high : SubRegIndex; -def subreg_low : SubRegIndex; +def subreg_32bit : SubRegIndex<32>; // could also be named "subreg_high32" +// Indices are used in a variety of ways, so don't set an Offset. +def subreg_high : SubRegIndex<64, -1>; +def subreg_low : SubRegIndex<64, -1>; def subreg_low32 : ComposedSubRegIndex; } diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp index 3eed3ffb5f4..daa7eab658d 100644 --- a/utils/TableGen/CodeGenRegisters.cpp +++ b/utils/TableGen/CodeGenRegisters.cpp @@ -1092,11 +1092,24 @@ getConcatSubRegIndex(const SmallVector &Parts) { // None exists, synthesize one. std::string Name = Parts.front()->getName(); + // Determine whether all parts are contiguous. + bool isContinuous = true; + unsigned Size = Parts.front()->Size; + unsigned LastOffset = Parts.front()->Offset; + unsigned LastSize = Parts.front()->Size; for (unsigned i = 1, e = Parts.size(); i != e; ++i) { Name += '_'; Name += Parts[i]->getName(); + Size += Parts[i]->Size; + if (Parts[i]->Offset != (LastOffset + LastSize)) + isContinuous = false; + LastOffset = Parts[i]->Offset; + LastSize = Parts[i]->Size; } - return Idx = createSubRegIndex(Name, Parts.front()->getNamespace()); + Idx = createSubRegIndex(Name, Parts.front()->getNamespace()); + Idx->Size = Size; + Idx->Offset = isContinuous ? Parts.front()->Offset : -1; + return Idx; } void CodeGenRegBank::computeComposites() { diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index c83455149a6..f9edc6553ac 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -37,10 +37,10 @@ namespace llvm { Record *const TheDef; std::string Name; std::string Namespace; - uint16_t Size; - uint16_t Offset; public: + uint16_t Size; + uint16_t Offset; const unsigned EnumValue; unsigned LaneMask; @@ -54,8 +54,6 @@ namespace llvm { const std::string &getName() const { return Name; } const std::string &getNamespace() const { return Namespace; } std::string getQualifiedName() const; - uint16_t getSize() const { return Size; } - uint16_t getOffset() const { return Offset; } // Order CodeGenSubRegIndex pointers by EnumValue. struct Less { diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 9978237a185..1a6cc3a01c2 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -798,8 +798,8 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, for (ArrayRef::const_iterator SRI = SubRegIndices.begin(), SRE = SubRegIndices.end(); SRI != SRE; ++SRI) { - OS << " { " << (*SRI)->getOffset() << ", " - << (*SRI)->getSize() + OS << " { " << (*SRI)->Offset << ", " + << (*SRI)->Size << " },\t// " << (*SRI)->getName() << "\n"; } OS << "};\n\n"; -- 2.34.1