From 24487e0ff9369ed19b830af9d22df8f09a963576 Mon Sep 17 00:00:00 2001 From: Luowei Date: Fri, 4 Jul 2014 18:27:32 +0800 Subject: [PATCH] add rk3036 pinctrl support --- arch/arm/boot/dts/rk3036-pinctrl.dtsi | 466 ++++++++++++++++++ arch/arm/boot/dts/rk3036-sdk.dts | 2 +- include/dt-bindings/pinctrl/rockchip-rk3036.h | 266 ++++++++++ 3 files changed, 733 insertions(+), 1 deletion(-) create mode 100755 arch/arm/boot/dts/rk3036-pinctrl.dtsi create mode 100644 include/dt-bindings/pinctrl/rockchip-rk3036.h diff --git a/arch/arm/boot/dts/rk3036-pinctrl.dtsi b/arch/arm/boot/dts/rk3036-pinctrl.dtsi new file mode 100755 index 000000000000..ed83553c5c15 --- /dev/null +++ b/arch/arm/boot/dts/rk3036-pinctrl.dtsi @@ -0,0 +1,466 @@ +#include +#include +#include +#include + +/ { + pinctrl: pinctrl@20008000 { + compatible = "rockchip,rk3036-pinctrl"; + reg = <0x20008000 0xA8>, + <0x200080A8 0x30>, + <0x20008118 0x18>, + <0x20008100 0x04>; + reg-names = "base", "mux", "pull", "drv"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@2007c000 { + compatible = "rockchip,rk3036-gpio-bank0"; + reg = <0x2007c000 0x100>, + <0x2007c000 0>; + + reg-names = "base", "pull_bank0"; + interrupts = ; + //clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + clocks = <&clk_gates8 10>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = ; + //clocks = <&clk_gates8 11>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio15: gpio15@20086000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20086000 0x100>; + interrupts = ;//127 = 160-32-1 + //clocks = <&clk_gates8 12>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg_pull_up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg_pull_down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; + + gpio1_uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = , + ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + uart0_cts: uart0-cts { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + uart0_rts: uart0-rts { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = ; + rockchip,drive = ; + }; + }; + + gpio1_uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = , + ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + }; + + gpio1_uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = , + ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + /* no rts / cts for uart2 */ + }; + + + gpio1_i2c0 { + i2c0_sda:i2c0-sda { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c0_scl:i2c0-scl { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c0_gpio: i2c0-gpio { + rockchip,pins = , ; + rockchip,drive = ; + }; + }; + + gpio1_i2c1 { + i2c1_sda:i2c1-sda { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c1_scl:i2c1-scl { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c1_gpio: i2c1-gpio { + rockchip,pins = , ; + rockchip,drive = ; + }; + }; + + gpio1_i2c2 { + i2c2_sda:i2c2-sda { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c2_scl:i2c2-scl { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + i2c2_gpio: i2c2-gpio { + rockchip,pins = , ; + rockchip,drive = ; + }; + }; + + + gpio1_spi0 { + spi0_txd:spi0-txd { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + spi0_rxd:spi0-rxd { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + spi0_clk:spi0-clk { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + spi0_cs0:spi0-cs0 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + spi0_cs1:spi0-cs1 { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + }; + + }; + + + gpio1_i2s0 { + + i2s0_mclk:i2s0-mclk { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s0_sclk:i2s0-sclk { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s0_lrckrx:i2s0-lrckrx { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s0_lrcktx:i2s0-lrcktx { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s0_sdo:i2s0-sdo { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s0_sdi:i2s0-sdi { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + + i2s0_gpio: i2s0-gpio { + rockchip,pins = , + , + , + , + , + ; + rockchip,drive = ; + }; + }; + + + gpio1_spdif { + spdif_tx: spdif-tx { + rockchip,pins = ; + rockchip,pull = ; + //rockchip,voltage = ; + rockchip,drive = ; + //rockchip,tristate = ; + + }; + }; + + + vol_domain { + ap0_vcc:ap0-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + ap1_vcc:ap1-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + cif_vcc:cif-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + flash_vcc:flash-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + vccio0_vcc:vccio0-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + vccio1_vcc:vccio1-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + lcdc0_vcc:lcdc0-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + lcdc1_vcc:lcdc1-vcc { + rockchip,pins = ; + rockchip,voltage = ; + }; + + + + ap0_vcc_18:ap0-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + ap1_vcc_18:ap1-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + cif_vcc_18:cif-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + flash_vcc_18:flash-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + vccio0_vcc_18:vccio0-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + vccio1_vcc_18:vccio1-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + lcdc0_vcc_18:lcdc0-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + lcdc1_vcc_18:lcdc1-vcc-18 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + + + ap0_vcc_33:ap0-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + ap1_vcc_33:ap1-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + cif_vcc_33:cif-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + flash_vcc_33:flash-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + vccio0_vcc_33:vccio0-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + vccio1_vcc_33:vccio1-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + lcdc0_vcc_33:lcdc0-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + lcdc1_vcc_33:lcdc1-vcc-33 { + rockchip,pins = ; + rockchip,voltage = ; + }; + + + }; + + //to add + }; +}; diff --git a/arch/arm/boot/dts/rk3036-sdk.dts b/arch/arm/boot/dts/rk3036-sdk.dts index d7c517491c6e..890a478570d6 100755 --- a/arch/arm/boot/dts/rk3036-sdk.dts +++ b/arch/arm/boot/dts/rk3036-sdk.dts @@ -1,7 +1,7 @@ /dts-v1/; #include "rk3036.dtsi" - +#include "rk3036-pinctrl.dtsi" / { fiq-debugger { diff --git a/include/dt-bindings/pinctrl/rockchip-rk3036.h b/include/dt-bindings/pinctrl/rockchip-rk3036.h new file mode 100644 index 000000000000..01bf49ed1b09 --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip-rk3036.h @@ -0,0 +1,266 @@ +#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3036_H__ +#define __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3036_H__ + + /* GPIO0_A */ + #define GPIO0_A0 0x0a00 + #define I2C0_SCL 0x0a01 + #define PWM1 0x0a02 + + #define GPIO0_A1 0x0a10 + #define I2C0_SDA 0x0a11 + #define PWM2 0x0a12 + + #define GPIO0_A2 0x0a20 + #define I2C1_SCL 0x0a21 + + #define GPIO0_A3 0x0a30 + #define I2C1_SDA 0x0a31 + + + /* GPIO0_B */ + #define GPIO0_B0 0x0b00 + #define MMC1_CMD 0x0b01 + #define I2S1_SDO 0x0b02 + + #define GPIO0_B1 0x0b10 + #define MMC1_CLKOUT 0x0b11 + #define I2S1_MCLK 0x0b12 + + #define GPIO0_B3 0x0b30 + #define MMC1_D0 0x0b31 + #define I2S1_LRCKRX 0x0b32 + + #define GPIO0_B4 0x0b40 + #define MMC1_D1 0x0b41 + #define I2S1_LRCKTX 0x0b42 + + #define GPIO0_B5 0x0b50 + #define MMC1_D2 0x0b51 + #define I2S1_SDI 0x0b52 + + #define GPIO0_B6 0x0b60 + #define MMC1_D3 0x0b61 + #define I2S1_SCLK 0x0b62 + + + /* GPIO0_C */ + #define GPIO0_C0 0x0c00 + #define UART0_SOUT 0x0c01 + + #define GPIO0_C1 0x0c10 + #define UART0_SIN 0x0c11 + + #define GPIO0_C2 0x0c20 + #define UART0_RTSN 0x0c21 + + #define GPIO0_C3 0x0c30 + #define UART0_CTSN 0x0c31 + + #define GPIO0_C4 0x0c40 + #define DRIVE_VBUS 0x0c41 + + + /* GPIO0_D */ + #define GPIO0_D2 0x0d20 + #define PWM0 0x0d21 + + #define GPIO0_D3 0x0d30 + #define PWM3(IR) 0x0d31 + + #define GPIO0_D4 0x0d40 + #define SPDIF_TX 0x0d41 + + + /* GPIO1_A */ + #define GPIO1_A0 0x1a00 + #define I2S0_MCLK 0x1a01 + + #define GPIO1_A1 0x1a10 + #define I2S0_SCLK 0x1a11 + + #define GPIO1_A2 0x1a20 + #define I2S0_LRCKRX 0x1a21 + #define PWM1_0 0x1a22 + + #define GPIO1_A3 0x1a30 + #define I2S0_LRCKTX 0x1a31 + + #define GPIO1_A4 0x1a40 + #define I2S0_SDO 0x1a41 + + #define GPIO1_A5 0x1a50 + #define I2S0_SDI 0x1a51 + + + /* GPIO1_B */ + #define GPIO1_B0 0x1b00 + #define HDMI_CEC 0x1b01 + + #define GPIO1_B1 0x1b10 + #define HDMI_SDA 0x1b11 + + #define GPIO1_B2 0x1b20 + #define HDMI_SCL 0x1b21 + + #define GPIO1_B3 0x1b30 + #define HDMI_HPD 0x1b31 + + #define GPIO1_B7 0x1b70 + #define MMC0_CMD 0x1b71 + + + /* GPIO1_C */ + #define GPIO1_C0 0x1c00 + #define MMC0_CLKOUT 0x1c01 + + #define GPIO1_C1 0x1c10 + #define MMC0_DETN 0x1c11 + + #define GPIO1_C2 0x1c20 + #define MMC0_D0 0x1c21 + #define UART2_SIN 0x1c22 + + #define GPIO1_C3 0x1c30 + #define MMC0_D1 0x1c31 + #define UART2_SOUT 0x1c32 + + #define GPIO1_C4 0x1c40 + #define MMC0_D2 0x1c41 + #define JTAG_TCK 0x1c42 + + #define GPIO1_C5 0x1c50 + #define MMC0_D3 0x1c51 + #define JTAG_TMS 0x1c52 + + + /* GPIO1_D */ + #define GPIO1_D0 0x1d00 + #define NAND_D0 0x1d01 + #define EMMC_D0 0x1d02 + #define SFC_SIO0 0x1d03 + + #define GPIO1_D1 0x1d10 + #define NAND_D1 0x1d11 + #define EMMC_D1 0x1d12 + #define SFC_SIO1 0x1d13 + + #define GPIO1_D2 0x1d20 + #define NAND_D2 0x1d21 + #define EMMC_D2 0x1d22 + #define SFC_SIO2 0x1d23 + + #define GPIO1_D3 0x1d30 + #define NAND_D3 0x1d31 + #define EMMC_D3 0x1d32 + #define SFC_SIO3 0x1d33 + + #define GPIO1_D4 0x1d40 + #define NAND_D4 0x1d41 + #define EMMC_D4 0x1d42 + #define SPI0_RXD 0x1d43 + + #define GPIO1_D5 0x1d50 + #define NAND_D5 0x1d51 + #define EMMC_D5 0x1d52 + #define SPI0_TXD 0x1d53 + + #define GPIO1_D6 0x1d60 + #define NAND_D6 0x1d61 + #define EMMC_D6 0x1d62 + #define SPI0_CS0 0x1d63 + + #define GPIO1_D7 0x1d70 + #define NAND_D7 0x1d71 + #define EMMC_D7 0x1d72 + #define SPI0_CS1 0x1d73 + + + /* GPIO2_A */ + #define GPIO2_A0 0x2a00 + #define NAND_ALE 0x2a01 + #define SPI0_CLK 0x2a02 + + #define GPIO2_A1 0x2a10 + #define NAND_CLE 0x2a11 + #define EMMC_CLKOUT 0x2a12 + + #define GPIO2_A2 0x2a20 + #define NAND_WRN 0x2a21 + #define SFC_CSN0 0x2a22 + + #define GPIO2_A3 0x2a30 + #define NAND_RDN 0x2a31 + #define SFC_CSN1 0x2a32 + + #define GPIO2_A4 0x2a40 + #define NAND_RDY 0x2a41 + #define EMMC_CMD 0x2a42 + #define SFC_CLK 0x2a43 + + #define GPIO2_A6 0x2a60 + #define NAND_CS0 0x2a61 + + #define GPIO2_A7 0x2a70 + #define TESTCLK_OUT 0x2a71 + + + /* GPIO2_B */ + #define GPIO2_B2 0x2b20 + #define MAC_CRS 0x2b21 + + #define GPIO2_B4 0x2b40 + #define MAC_MDIO 0x2b41 + + #define GPIO2_B5 0x2b50 + #define MAC_TXEN 0x2b51 + + #define GPIO2_B6 0x2b60 + #define MAC_CLKOUT 0x2b61 + #define MAC_CLKIN 0x2b62 + + #define GPIO2_B7 0x2b70 + #define MAC_RXER 0x2b71 + + + /* GPIO2_C */ + #define GPIO2_C0 0x2c00 + #define MAC_RXD1 0x2c01 + + #define GPIO2_C1 0x2c10 + #define MAC_RXD0 0x2c11 + + #define GPIO2_C2 0x2c20 + #define MAC_TXD1 0x2c21 + + #define GPIO2_C3 0x2c30 + #define MAC_TXD0 0x2c31 + + #define GPIO2_C4 0x2c40 + #define I2C2_SDA 0x2c41 + + #define GPIO2_C5 0x2c50 + #define I2C2_SCL 0x2c51 + + #define GPIO2_C6 0x2c60 + #define UART1_SIN 0x2c61 + + #define GPIO2_C7 0x2c70 + #define UART1_SOUT 0x2c71 + #define TESTCLK_OUT1 0x2c72 + + + /* GPIO2_D */ + #define GPIO2_D1 0x2d10 + #define MAC_MDC 0x2d11 + + #define GPIO2_D4 0x2d40 + #define I2S0_SDO3 0x2d41 + + #define GPIO2_D5 0x2d50 + #define I2S0_SDO2 0x2d51 + + #define GPIO2_D6 0x2d60 + #define I2S0_SDO1 0x2d61 + + +#endif -- 2.34.1