From 259b76dfeaf69a2e4d0a8d554394354e8b5fa4a9 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 11 Nov 2015 00:01:32 +0000 Subject: [PATCH] AMDGPU: Set isAllocatable = 0 on VS_32/VS_64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252674 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIRegisterInfo.cpp | 8 +------- lib/Target/AMDGPU/SIRegisterInfo.h | 7 ------- lib/Target/AMDGPU/SIRegisterInfo.td | 7 +++++-- test/CodeGen/AMDGPU/ftrunc.f64.ll | 4 ++-- test/CodeGen/AMDGPU/llvm.round.f64.ll | 2 +- 5 files changed, 9 insertions(+), 19 deletions(-) diff --git a/lib/Target/AMDGPU/SIRegisterInfo.cpp b/lib/Target/AMDGPU/SIRegisterInfo.cpp index 436808b5287..78231d79f6b 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -79,8 +79,6 @@ unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF, STI.getMaxWavesPerCU()); unsigned VGPRLimit = getNumVGPRsAllowed(STI.getMaxWavesPerCU()); - unsigned VSLimit = SGPRLimit + VGPRLimit; - for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) { const TargetRegisterClass *RC = *I; @@ -88,11 +86,7 @@ unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF, unsigned NumSubRegs = std::max((int)RC->getSize() / 4, 1); unsigned Limit; - if (isPseudoRegClass(RC)) { - // FIXME: This is a hack. We should never be considering the pressure of - // these since no virtual register should ever have this class. - Limit = VSLimit; - } else if (isSGPRClass(RC)) { + if (isSGPRClass(RC)) { Limit = SGPRLimit / NumSubRegs; } else { Limit = VGPRLimit / NumSubRegs; diff --git a/lib/Target/AMDGPU/SIRegisterInfo.h b/lib/Target/AMDGPU/SIRegisterInfo.h index b1389533ec3..3458cec0923 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/lib/Target/AMDGPU/SIRegisterInfo.h @@ -59,13 +59,6 @@ public: /// \returns true if this class contains VGPR registers. bool hasVGPRs(const TargetRegisterClass *RC) const; - /// returns true if this is a pseudoregister class combination of VGPRs and - /// SGPRs for operand modeling. FIXME: We should set isAllocatable = 0 on - /// them. - static bool isPseudoRegClass(const TargetRegisterClass *RC) { - return RC == &AMDGPU::VS_32RegClass || RC == &AMDGPU::VS_64RegClass; - } - /// \returns A VGPR reg class with the same width as \p SRC const TargetRegisterClass *getEquivalentVGPRClass( const TargetRegisterClass *SRC) const; diff --git a/lib/Target/AMDGPU/SIRegisterInfo.td b/lib/Target/AMDGPU/SIRegisterInfo.td index e28dd2fdf91..93909cf2fad 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/lib/Target/AMDGPU/SIRegisterInfo.td @@ -272,9 +272,12 @@ def SCSrc_32 : RegInlineOperand { // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate //===----------------------------------------------------------------------===// -def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>; +def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SReg_32, VGPR_32)> { + let isAllocatable = 0; +} -def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> { +def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add SReg_64, VReg_64)> { + let isAllocatable = 0; let CopyCost = 2; } diff --git a/test/CodeGen/AMDGPU/ftrunc.f64.ll b/test/CodeGen/AMDGPU/ftrunc.f64.ll index 83a8ad8901d..500cbf4747f 100644 --- a/test/CodeGen/AMDGPU/ftrunc.f64.ll +++ b/test/CodeGen/AMDGPU/ftrunc.f64.ll @@ -27,8 +27,8 @@ define void @v_ftrunc_f64(double addrspace(1)* %out, double addrspace(1)* %in) { ; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 ; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01 ; SI: s_lshr_b64 -; SI: s_not_b64 -; SI: s_and_b64 +; SI-DAG: s_not_b64 +; SI-DAG: s_and_b64 ; SI-DAG: cmp_gt_i32 ; SI-DAG: cndmask_b32 ; SI-DAG: cndmask_b32 diff --git a/test/CodeGen/AMDGPU/llvm.round.f64.ll b/test/CodeGen/AMDGPU/llvm.round.f64.ll index 6b365dc09e2..98afbeee93e 100644 --- a/test/CodeGen/AMDGPU/llvm.round.f64.ll +++ b/test/CodeGen/AMDGPU/llvm.round.f64.ll @@ -21,7 +21,7 @@ define void @round_f64(double addrspace(1)* %out, double %x) #0 { ; SI-DAG: v_cmp_eq_i32 ; SI-DAG: s_mov_b32 [[BFIMASK:s[0-9]+]], 0x7fffffff -; SI-DAG: v_cmp_gt_i32_e32 +; SI-DAG: v_cmp_gt_i32 ; SI-DAG: v_bfi_b32 [[COPYSIGN:v[0-9]+]], [[BFIMASK]] ; SI: buffer_store_dwordx2 -- 2.34.1