From 25f0664f67ce4f87a330eeca8d808984b1fc3a91 Mon Sep 17 00:00:00 2001
From: Jung Zhao <jung.zhao@rock-chips.com>
Date: Mon, 20 Mar 2017 11:14:27 +0800
Subject: [PATCH] ARM64: dts: rk3368: add vpu & hevc node

Change-Id: Iee8fb808ad0c929be8fa5db8164fd6e05321b352
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 52 ++++++++++++++++++++++--
 1 file changed, 48 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index cb0bac5be2c6..91b8f27b6c3c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -1252,8 +1252,8 @@
 
 	hevc_mmu: iommu@ff9a0440 {
 		compatible = "rockchip,iommu";
-		reg = <0x0 0xff9a0440 0x0 0x100>,
-		      <0x0 0xff9a0480 0x0 0x100>;
+		reg = <0x0 0xff9a0440 0x0 0x40>,
+		      <0x0 0xff9a0480 0x0 0x40>;
 		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "hevc_mmu";
 		clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
@@ -1266,8 +1266,9 @@
 	vpu_mmu: iommu@ff9a0800 {
 		compatible = "rockchip,iommu";
 		reg = <0x0 0xff9a0800 0x0 0x100>;
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "vpu_mmu";
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vepu_mmu", "vdpu_mmu";
 		clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
 		clock-names = "aclk", "hclk";
 		power-domains = <&power RK3368_PD_VIDEO>;
@@ -1275,6 +1276,49 @@
 		status = "disabled";
 	};
 
+	vpu: vpu_service {
+		compatible = "rockchip,vpu_sub";
+		iommu_enabled = <1>;
+		iommus = <&vpu_mmu>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_enc","irq_dec";
+		dev_mode = <0>;
+		name = "vpu_service";
+		allocator = <1>;
+	};
+
+	hevc: hevc_service {
+		compatible = "rockchip,hevc_sub";
+		iommu_enabled = <1>;
+		iommus = <&hevc_mmu>;
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_dec";
+		dev_mode = <1>;
+		name = "hevc_service";
+		allocator = <1>;
+	};
+
+	vpu_combo: vpu_combo@ff9a0000 {
+		compatible = "rockchip,vpu_combo";
+		reg = <0x0 0xff9a0000 0x0 0x440>;
+		rockchip,grf = <&grf>;
+		subcnt = <2>;
+		rockchip,sub = <&vpu>, <&hevc>;
+		clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
+			 <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
+		clock-names = "aclk_vcodec", "hclk_vcodec",
+			      "clk_core", "clk_cabac";
+		resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
+			 <&cru SRST_VIDEO>;
+		reset-names = "video_a", "video_h", "video";
+		mode_bit = <12>;
+		mode_ctrl = <0x418>;
+		name = "vpu_combo";
+		power-domains = <&power RK3368_PD_VIDEO>;
+		status = "disabled";
+	};
+
 	gic: interrupt-controller@ffb71000 {
 		compatible = "arm,gic-400";
 		interrupt-controller;
-- 
2.34.1