From 27539d46ccde86358f32226907149083d7a4dcf7 Mon Sep 17 00:00:00 2001 From: Louis Gerbarg Date: Mon, 14 Apr 2014 21:05:02 +0000 Subject: [PATCH] Add a flag to disable the ARM64DeadRegisterDefinitionsPass This patch adds a -arm64-dead-def-elimination flag so that it is possible to disable dead definition elimination. Includes test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206207 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM64/ARM64TargetMachine.cpp | 11 ++++++++++- .../ARM64/arm64-dead-def-elimination-flag.ll | 16 ++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/ARM64/arm64-dead-def-elimination-flag.ll diff --git a/lib/Target/ARM64/ARM64TargetMachine.cpp b/lib/Target/ARM64/ARM64TargetMachine.cpp index 101dc25839e..f4a79963790 100644 --- a/lib/Target/ARM64/ARM64TargetMachine.cpp +++ b/lib/Target/ARM64/ARM64TargetMachine.cpp @@ -39,6 +39,14 @@ EnableCollectLOH("arm64-collect-loh", cl::Hidden, " optimization hints (LOH)"), cl::init(true)); +static cl::opt +EnableDeadRegisterElimination("arm64-dead-def-elimination", cl::Hidden, + cl::desc("Enable the pass that removes dead" + " definitons and replaces stores to" + " them with stores to the zero" + " register"), + cl::init(true)); + extern "C" void LLVMInitializeARM64Target() { // Register the target. RegisterTargetMachine X(TheARM64Target); @@ -135,7 +143,8 @@ bool ARM64PassConfig::addPreRegAlloc() { bool ARM64PassConfig::addPostRegAlloc() { // Change dead register definitions to refer to the zero register. - addPass(createARM64DeadRegisterDefinitions()); + if (EnableDeadRegisterElimination) + addPass(createARM64DeadRegisterDefinitions()); return true; } diff --git a/test/CodeGen/ARM64/arm64-dead-def-elimination-flag.ll b/test/CodeGen/ARM64/arm64-dead-def-elimination-flag.ll new file mode 100644 index 00000000000..babf4827693 --- /dev/null +++ b/test/CodeGen/ARM64/arm64-dead-def-elimination-flag.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=arm64 -arm64-dead-def-elimination=false < %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-ios7.0.0" + +; Function Attrs: nounwind ssp uwtable +define i32 @test1() #0 { + %tmp1 = alloca i8 + %tmp2 = icmp eq i8* %tmp1, null + %tmp3 = zext i1 %tmp2 to i32 + + ret i32 %tmp3 + + ; CHECK-LABEL: test1 + ; CHECK: adds {{x[0-9]+}}, sp, #15 +} -- 2.34.1