From 275944afb55086d0b4b20d4d831de7c1c7507925 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 25 Jul 2011 21:32:49 +0000 Subject: [PATCH] Fix more MC layering violations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135979 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 8eeca013ffb..6883fcbe2e3 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -153,6 +153,11 @@ public: }; } // end anonymous namespace +namespace llvm { + // FIXME: TableGen this? + extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc. +} + namespace { /// ARMOperand - Instances of this class represent a parsed ARM machine @@ -971,9 +976,11 @@ public: SMLoc StartLoc, SMLoc EndLoc) { KindTy Kind = RegisterList; - if (ARM::DPRRegClass.contains(Regs.front().first)) + if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID]. + contains(Regs.front().first)) Kind = DPRRegisterList; - else if (ARM::SPRRegClass.contains(Regs.front().first)) + else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID]. + contains(Regs.front().first)) Kind = SPRRegisterList; ARMOperand *Op = new ARMOperand(Kind); -- 2.34.1