From 28905e328bce30be47d333bc3ae062fdc2ffcd55 Mon Sep 17 00:00:00 2001 From: chenxing Date: Fri, 10 May 2013 18:06:04 +0800 Subject: [PATCH] rk3066B: compatible with rk3188 plus pll config, fix compile error --- arch/arm/mach-rk30/include/mach/cru-rk3066b.h | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-rk30/include/mach/cru-rk3066b.h b/arch/arm/mach-rk30/include/mach/cru-rk3066b.h index bd7ea8e36dfd..f9da1ab20434 100755 --- a/arch/arm/mach-rk30/include/mach/cru-rk3066b.h +++ b/arch/arm/mach-rk30/include/mach/cru-rk3066b.h @@ -71,19 +71,16 @@ enum rk_plls_id { #define PLL_CLKF_SET(val) (PLL_CLKF(val) | CRU_W_MSK(PLL_NF_SHIFT, PLL_NF_MSK)) /*******************PLL CON2 BITS***************************/ -#if 0 -#define PLL_BWADJ_MSK (0xfff) +// "BWADJ" Just compatible with RK3188 plus +#define PLL_BWADJ_MSK (0xfff & 0x000) #define PLL_BWADJ_SHIFT (0) #define PLL_CLK_BWADJ_SET(val) ((val) | CRU_W_MSK(PLL_BWADJ_SHIFT, PLL_BWADJ_MSK)) -#endif /*******************PLL CON3 BITS***************************/ - -#if 0 -#define PLL_REST_MSK (1 << 5) -#define PLL_REST_W_MSK (PLL_REST_MSK << 16) -#define PLL_REST (1 << 5) -#define PLL_REST_RESM (0 << 5) -#endif +// "RESET" Just compatible with RK3188 plus +#define PLL_RESET_MSK ((1 & 0x0) << 5) +#define PLL_RESET_W_MSK (PLL_RESET_MSK << 16) +#define PLL_RESET (1 << 5) +#define PLL_RESET_RESUME (0 << 5) #define PLL_BYPASS_MSK (1 << 0) #define PLL_BYPASS (1 << 0) -- 2.34.1