From 29467e755f7dad25d9b0884316151f9bcad469ee Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 2 Oct 2015 18:58:37 +0000 Subject: [PATCH] AMDGPU/SI: Add verifier check for exec reads Make sure we aren't accidentally not setting these in the instruction definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249170 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIInstrInfo.cpp | 10 ++++++++++ lib/Target/AMDGPU/SIInstructions.td | 6 ++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp index 85c1e9179c9..122b65b042b 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1445,6 +1445,16 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI, } } + // Make sure we aren't losing exec uses in the td files. This mostly requires + // being careful when using let Uses to try to add other use registers. + if (!isGenericOpcode(Opcode) && !isSALU(Opcode) && !isSMRD(Opcode)) { + const MachineOperand *Exec = MI->findRegisterUseOperand(AMDGPU::EXEC); + if (!Exec || !Exec->isImplicit()) { + ErrInfo = "VALU instruction does not implicitly read exec mask"; + return false; + } + } + return true; } diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td index 2a5047759b7..31768b75597 100644 --- a/lib/Target/AMDGPU/SIInstructions.td +++ b/lib/Target/AMDGPU/SIInstructions.td @@ -1859,7 +1859,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in { def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$dst), (ins VSrc_64:$src0), "", []>; } // end let hasSideEffects = 0, mayLoad = 0, mayStore = 0 -let hasSideEffects = 1 in { +let hasSideEffects = 1, SALU = 1 in { def SGPR_USE : InstSI <(outs),(ins), "", []>; } @@ -2062,7 +2062,9 @@ def SI_CONSTDATA_PTR : InstSI < (outs SReg_64:$dst), (ins), "", [(set SReg_64:$dst, (i64 SIconstdata_ptr))] ->; +> { + let SALU = 1; +} } // End Defs = [SCC] -- 2.34.1