From 2a9f4cb9dedfddfc5b1834190c34a69255d43c50 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=E9=99=88=E4=BA=AE?= <cl@rock-chips.com>
Date: Tue, 1 Apr 2014 03:13:41 -0700
Subject: [PATCH] rk3288-tb: adjust clk core dvfs table; init vdd_logic by ddr
 dvfs table

---
 arch/arm/boot/dts/rk3288-tb.dts    | 16 ++++++++++++----
 arch/arm/boot/dts/rk3288.dtsi      |  2 +-
 arch/arm/mach-rockchip/ddr_freq.c  |  2 +-
 arch/arm/mach-rockchip/dvfs.c      |  2 +-
 arch/arm/mach-rockchip/rk3188.c    | 12 +++++++-----
 drivers/clk/rockchip/clk-ops.c     |  2 +-
 drivers/cpufreq/rockchip-cpufreq.c |  6 ++++++
 7 files changed, 29 insertions(+), 13 deletions(-)

diff --git a/arch/arm/boot/dts/rk3288-tb.dts b/arch/arm/boot/dts/rk3288-tb.dts
index ecafd2422d9c..3297386002c1 100755
--- a/arch/arm/boot/dts/rk3288-tb.dts
+++ b/arch/arm/boot/dts/rk3288-tb.dts
@@ -571,13 +571,18 @@ rockchip,power_type = <GPIO>;
 &clk_core_dvfs_table {
 	operating-points = <
 		/* KHz    uV */
+		126000 850000
+		216000 850000
 		312000 850000
-		504000 850000
+		408000 850000
+		600000 850000
+		696000 900000
 		816000 950000
 		1008000 1000000
 		1200000 1050000
 		1416000 1150000
 		>;
+	status="okay";
 };
 
 &clk_gpu_dvfs_table {
@@ -589,14 +594,16 @@ rockchip,power_type = <GPIO>;
 		400000 1000000
 		600000 1250000
 		>;
+	status="okay";
 };
 
 &clk_ddr_dvfs_table {
 	operating-points = <
 		/* KHz    uV */
-		200000 1200000
-		300000 1200000
-		400000 1200000
+		200000 950000
+		300000 950000
+		400000 1000000
+		533000 1050000
 		>;
 
 	freq_table = <
@@ -606,6 +613,7 @@ rockchip,power_type = <GPIO>;
 		SYS_STATUS_VIDEO	300000
 		SYS_STATUS_DUALVIEW	500000
 		>;
+	status="okay";
 };
 
 /include/ "rk808.dtsi"
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index aa3b31612a4a..eaf4c1f7d352 100755
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -879,7 +879,7 @@
 						300000 1300000
 						400000 1300000
 						>;
-					status = "okay";
+					status = "disable";
 				};
 			};
 		};
diff --git a/arch/arm/mach-rockchip/ddr_freq.c b/arch/arm/mach-rockchip/ddr_freq.c
index 3dee44c44d3e..43bc2e358f6b 100644
--- a/arch/arm/mach-rockchip/ddr_freq.c
+++ b/arch/arm/mach-rockchip/ddr_freq.c
@@ -433,4 +433,4 @@ err:
 
 	return ret;
 }
-late_initcall(ddrfreq_init);
+//late_initcall(ddrfreq_init);
diff --git a/arch/arm/mach-rockchip/dvfs.c b/arch/arm/mach-rockchip/dvfs.c
index 7e4e2e7b25e5..25f52fbee2cc 100644
--- a/arch/arm/mach-rockchip/dvfs.c
+++ b/arch/arm/mach-rockchip/dvfs.c
@@ -633,7 +633,7 @@ int clk_enable_dvfs(struct dvfs_node *clk_dvfs_node)
 		clk_dvfs_node->freq_limit_en = 1;
 		dvfs_table_round_volt(clk_dvfs_node);
 		clk_dvfs_node->set_freq = clk_dvfs_node_get_rate_kz(clk_dvfs_node->clk);
-		clk_dvfs_node->last_set_rate = clk_dvfs_node->set_freq;
+		clk_dvfs_node->last_set_rate = clk_dvfs_node->set_freq*1000;
 		
 		DVFS_DBG("%s: %s get freq %u!\n", 
 			__func__, clk_dvfs_node->name, clk_dvfs_node->set_freq);
diff --git a/arch/arm/mach-rockchip/rk3188.c b/arch/arm/mach-rockchip/rk3188.c
index 79c53e221cc4..18b1dd296fb3 100644
--- a/arch/arm/mach-rockchip/rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188.c
@@ -371,12 +371,14 @@ static void __init rk3188_init_suspend(void)
 
 static int __init rk3188_ddr_init(void)
 {
-	ddr_change_freq = _ddr_change_freq;
-	ddr_round_rate = _ddr_round_rate;
-	ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
-	
-	if (cpu_is_rk3188())
+	if (cpu_is_rk3188()) {
+
+		ddr_change_freq = _ddr_change_freq;
+		ddr_round_rate = _ddr_round_rate;
+		ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
+
 		ddr_init(DDR3_DEFAULT, 300);
+	}
 
 	return 0;
 }
diff --git a/drivers/clk/rockchip/clk-ops.c b/drivers/clk/rockchip/clk-ops.c
index 3b59e3def34f..8a803bd6d5cc 100644
--- a/drivers/clk/rockchip/clk-ops.c
+++ b/drivers/clk/rockchip/clk-ops.c
@@ -425,7 +425,7 @@ static long clk_ddr_determine_rate(struct clk_hw *hw, unsigned long rate,
 
 	if (!ddr_round_rate) {
 		/* Do nothing before ddr init */
-		best = __clk_get_rate(hw->clk);
+		best = rate;//__clk_get_rate(hw->clk);
 	} else {
 		/* Func provided by ddr driver */
 		best = ddr_round_rate(rate/MHZ) * MHZ;
diff --git a/drivers/cpufreq/rockchip-cpufreq.c b/drivers/cpufreq/rockchip-cpufreq.c
index 473ac4a48080..b0676fa3a04b 100644
--- a/drivers/cpufreq/rockchip-cpufreq.c
+++ b/drivers/cpufreq/rockchip-cpufreq.c
@@ -74,6 +74,7 @@ static bool gpu_is_mali400;
 struct dvfs_node *clk_cpu_dvfs_node = NULL;
 struct dvfs_node *clk_gpu_dvfs_node = NULL;
 struct dvfs_node *clk_vepu_dvfs_node = NULL;
+struct dvfs_node *clk_ddr_dvfs_node = NULL;
 /*******************************************************/
 static unsigned int cpufreq_get_rate(unsigned int cpu)
 {
@@ -183,6 +184,11 @@ static int cpufreq_init_cpu0(struct cpufreq_policy *policy)
 		clk_enable_dvfs(clk_vepu_dvfs_node);
 	}
 
+	clk_ddr_dvfs_node = clk_get_dvfs_node("clk_ddr");
+	if (clk_ddr_dvfs_node){
+		clk_enable_dvfs(clk_ddr_dvfs_node);
+	}
+
 	clk_cpu_dvfs_node = clk_get_dvfs_node("clk_core");
 	if (!clk_cpu_dvfs_node){
 		return -EINVAL;
-- 
2.34.1