From 2ad9f17fee5d6395cd8db81668853e6dbf94060b Mon Sep 17 00:00:00 2001 From: Jim Laskey Date: Thu, 22 Feb 2007 14:56:36 +0000 Subject: [PATCH] Simplify lowering and selection of exception ops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34488 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/MRegisterInfo.h | 8 ----- lib/Target/ARM/ARMISelLowering.cpp | 3 -- lib/Target/Alpha/AlphaISelLowering.cpp | 3 -- lib/Target/IA64/IA64ISelLowering.cpp | 3 -- lib/Target/PowerPC/PPCISelLowering.cpp | 49 ++++++++------------------ lib/Target/Sparc/SparcISelDAGToDAG.cpp | 3 -- lib/Target/X86/X86ISelLowering.cpp | 3 -- 7 files changed, 15 insertions(+), 57 deletions(-) diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h index 3e38ccc6c79..b3ec569aca5 100644 --- a/include/llvm/Target/MRegisterInfo.h +++ b/include/llvm/Target/MRegisterInfo.h @@ -470,14 +470,6 @@ public: /// address can be found. virtual unsigned getRARegister() const = 0; - /// getEHExceptionRegister - This method should return the register containing - /// the address of the exception info on entry to a landing pad. - virtual unsigned getEHExceptionRegister() const = 0; - - /// getEHHandlerRegister - This method should return the register containing - /// the switch table selection on entry to an landing pad. - virtual unsigned getEHHandlerRegister() const = 0; - /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. /// Subclasses should override this method for special handling of frame diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 37b1febd1f7..90d02b82cf6 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -1190,9 +1190,6 @@ SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { return LowerFORMAL_ARGUMENTS(Op, DAG); case ISD::RETURNADDR: break; case ISD::FRAMEADDR: break; - // Exception address and exception selector. Currently unimplemented. - case ISD::EXCEPTIONADDR: break; - case ISD::EHSELECTION: break; } return SDOperand(); } diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 12b299aeda6..1e7c79f9829 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -548,9 +548,6 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64); //FIXME: implement case ISD::FRAMEADDR: break; - // Exception address and exception selector. Currently unimplemented. - case ISD::EXCEPTIONADDR: break; - case ISD::EHSELECTION: break; } return SDOperand(); diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index 9a1c57bace3..1c7c51db0d1 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -590,9 +590,6 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: break; case ISD::FRAMEADDR: break; - // Exception address and exception selector. Currently unimplemented. - case ISD::EXCEPTIONADDR: break; - case ISD::EHSELECTION: break; } return SDOperand(); } diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 9c2867e87ad..342dd46ae28 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -140,14 +140,18 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) // We cannot sextinreg(i1). Expand to shifts. setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); - - + // Support label based line numbers. setOperationAction(ISD::LOCATION, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); - // FIXME - use subtarget debug flags - if (!TM.getSubtarget().isDarwin()) + if (!TM.getSubtarget().isDarwin()) { setOperationAction(ISD::LABEL, MVT::Other, Expand); + } else { + setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); + setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); + setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); + setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); + } // We want to legalize GlobalAddress and ConstantPool nodes into the // appropriate instructions to materialize the address. @@ -283,10 +287,15 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setShiftAmountType(MVT::i32); setSetCCResultContents(ZeroOrOneSetCCResult); - if (TM.getSubtarget().isPPC64()) + if (TM.getSubtarget().isPPC64()) { setStackPointerRegisterToSaveRestore(PPC::X1); - else + setExceptionPointerRegister(PPC::X3); + setExceptionSelectorRegister(PPC::X4); + } else { setStackPointerRegisterToSaveRestore(PPC::R1); + setExceptionPointerRegister(PPC::R3); + setExceptionSelectorRegister(PPC::R4); + } // We have target-specific dag combine patterns for the following nodes: setTargetDAGCombine(ISD::SINT_TO_FP); @@ -2610,30 +2619,6 @@ static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { } } -/// LowerEXCEPTIONADDR - Replace EXCEPTIONADDR with a copy from the exception -/// register. The register was made live in the ISel. -static SDOperand LowerEXCEPTIONADDR(SDOperand Op, SelectionDAG &DAG) { - const MRegisterInfo *MRI = DAG.getTargetLoweringInfo(). - getTargetMachine(). - getRegisterInfo(); - MVT::ValueType VT = Op.Val->getValueType(0); - unsigned Reg = MRI->getEHExceptionRegister(); - SDOperand Result = DAG.getCopyFromReg(Op.getOperand(0), Reg, VT); - return Result.getValue(Op.ResNo); -} - -/// LowerEXCEPTIONADDR - Replace EHSELECTION with a copy from the exception -/// selection register. The register was made live in the ISel. -static SDOperand LowerEHSELECTION(SDOperand Op, SelectionDAG &DAG) { - const MRegisterInfo *MRI = DAG.getTargetLoweringInfo(). - getTargetMachine(). - getRegisterInfo(); - MVT::ValueType VT = Op.Val->getValueType(0); - unsigned Reg = MRI->getEHHandlerRegister(); - SDOperand Result = DAG.getCopyFromReg(Op.getOperand(1), Reg, VT); - return Result.getValue(Op.ResNo); -} - /// LowerOperation - Provide custom lowering hooks for some operations. /// SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { @@ -2671,10 +2656,6 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: break; case ISD::FRAMEADDR: break; - - // Exception address and exception selector. - case ISD::EXCEPTIONADDR: return LowerEXCEPTIONADDR(Op, DAG); - case ISD::EHSELECTION: return LowerEHSELECTION(Op, DAG); } return SDOperand(); } diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 59c7901ab4b..647007e86bf 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -871,9 +871,6 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: break; case ISD::FRAMEADDR: break; - // Exception address and exception selector. Currently unimplemented. - case ISD::EXCEPTIONADDR: break; - case ISD::EHSELECTION: break; } return SDOperand(); } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 801c22d62b5..9371407f1cf 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -4675,9 +4675,6 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); - // Exception address and exception selector. Currently unimplemented. - case ISD::EXCEPTIONADDR: break; - case ISD::EHSELECTION: break; } return SDOperand(); } -- 2.34.1