From 2cb01afbb19cf3ea97ace14d62a3b56ffa37ad2f Mon Sep 17 00:00:00 2001
From: xiaoyao <xiaoyao@rock-chips.com>
Date: Thu, 15 Oct 2015 17:00:37 +0800
Subject: [PATCH] ARM: rk3228: dtsi: add SDCard/SDIO/eMMC DTS node for RK3228
 Chip

Change-Id: I172bceadc7bb4a09394837fd6bb81bbbedd7ddae
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
---
 arch/arm/boot/dts/rk3228.dtsi | 45 +++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi
index 503a4dd46736..e109f2729be3 100644
--- a/arch/arm/boot/dts/rk3228.dtsi
+++ b/arch/arm/boot/dts/rk3228.dtsi
@@ -356,4 +356,49 @@
 		clock-names = "pclk_vdac";
 		status = "disabled";
 	};
+
+	emmc: rksdmmc@30020000 {
+		compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
+		reg = <0x30020000 0x10000>;
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&clk_emmc>, <&clk_gates7 0>;
+		clock-names = "clk_mmc", "hclk_mmc";
+		num-slots = <1>;
+		fifo-depth = <0x100>;
+		bus-width = <8>;
+		cru_regsbase = <0x124>;
+		cru_reset_offset = <3>;
+	};
+
+	sdmmc: rksdmmc@30000000 {
+		compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
+		reg = <0x30000000 0x10000>;
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
+		clock-names = "clk_mmc", "hclk_mmc";
+		num-slots = <1>;
+		fifo-depth = <0x100>;
+		bus-width = <4>;
+		cru_regsbase = <0x124>;
+		cru_reset_offset = <1>;
+	};
+
+	sdio: rksdmmc@30010000 {
+		compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
+		reg = <0x30010000 0x10000>;
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&clk_sdio>, <&clk_gates5 11>;
+		clock-names = "clk_mmc", "hclk_mmc";
+		num-slots = <1>;
+		fifo-depth = <0x100>;
+		bus-width = <4>;
+		cru_regsbase = <0x124>;
+		cru_reset_offset = <2>;
+	};
  };
-- 
2.34.1