From 2e1334977408d524b9e96066d60fd1f6e1601144 Mon Sep 17 00:00:00 2001 From: Matthew Simpson Date: Wed, 18 Nov 2015 18:03:06 +0000 Subject: [PATCH] [Aarch64] Add cost for missing extensions. This patch adds a cost estimate for some missing sign and zero extensions. The costs were determined by counting the number of shift instructions generated without context for each new extension. Differential Revision: http://reviews.llvm.org/D14730 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253482 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../AArch64/AArch64TargetTransformInfo.cpp | 35 ++++++++++--------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index ab17bb810d4..81402a854f6 100644 --- a/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -188,28 +188,29 @@ int AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { static const TypeConversionCostTblEntry ConversionTbl[] = { - { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, - { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, - { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, - { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, - { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, - { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, + { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, + { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, + { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, + { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, // The number of shll instructions for the extension. - { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, - { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, - { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, - { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, - { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, - { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, - { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, - { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, + { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, + { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, + { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, + { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, + { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, + { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, + { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, + { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, + { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, + { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, + { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, + { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, + { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, - { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, - { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, - // LowerVectorINT_TO_FP: { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, -- 2.34.1