From 2f547971d3d195e734e60141676b83046f94b381 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Sun, 25 Mar 2012 11:24:53 +0800 Subject: [PATCH] rk30: clock: fix sdmmc and serial name --- arch/arm/mach-rk30/clock_data.c | 45 ++++++++++++++++----------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/arch/arm/mach-rk30/clock_data.c b/arch/arm/mach-rk30/clock_data.c index eb42ef651fc6..72f4bbfcef80 100644 --- a/arch/arm/mach-rk30/clock_data.c +++ b/arch/arm/mach-rk30/clock_data.c @@ -2371,34 +2371,33 @@ static struct clk_lookup clks[] = { CLK1(smc), CLK1(aclk_smc), - - CLK1(sdmmc), - CLK1(hclk_sdmmc), - - CLK1(sdio), - CLK1(hclk_sdio), - + + CLK("rk29_sdmmc.0", "mmc", &clk_sdmmc), + CLK("rk29_sdmmc.0", "hclk_mmc", &clk_hclk_sdmmc), + CLK("rk29_sdmmc.1", "mmc", &clk_sdio), + CLK("rk29_sdmmc.1", "hclk_mmc", &clk_hclk_sdio), + CLK1(emmc), CLK1(hclk_emmc), CLK1(uart_pll), - CLK("rk30_serial.0", "uart_div", &clk_uart0_div), - CLK("rk30_serial.0", "uart_frac_div", &clk_uart0_frac_div), - CLK("rk30_serial.0", "uart", &clk_uart0), - CLK("rk30_serial.0", "pclk_uart", &clk_pclk_uart0), - CLK("rk30_serial.1", "uart_div", &clk_uart1_div), - CLK("rk30_serial.1", "uart_frac_div", &clk_uart1_frac_div), - CLK("rk30_serial.1", "uart", &clk_uart1), - CLK("rk30_serial.1", "pclk_uart", &clk_pclk_uart1), - CLK("rk30_serial.2", "uart_div", &clk_uart2_div), - CLK("rk30_serial.2", "uart_frac_div", &clk_uart2_frac_div), - CLK("rk30_serial.2", "uart", &clk_uart2), - CLK("rk30_serial.2", "pclk_uart", &clk_pclk_uart2), - CLK("rk30_serial.3", "uart_div", &clk_uart3_div), - CLK("rk30_serial.3", "uart_frac_div", &clk_uart3_frac_div), - CLK("rk30_serial.3", "uart", &clk_uart3), - CLK("rk30_serial.3", "pclk_uart", &clk_pclk_uart3), + CLK("rk_serial.0", "uart_div", &clk_uart0_div), + CLK("rk_serial.0", "uart_frac_div", &clk_uart0_frac_div), + CLK("rk_serial.0", "uart", &clk_uart0), + CLK("rk_serial.0", "pclk_uart", &clk_pclk_uart0), + CLK("rk_serial.1", "uart_div", &clk_uart1_div), + CLK("rk_serial.1", "uart_frac_div", &clk_uart1_frac_div), + CLK("rk_serial.1", "uart", &clk_uart1), + CLK("rk_serial.1", "pclk_uart", &clk_pclk_uart1), + CLK("rk_serial.2", "uart_div", &clk_uart2_div), + CLK("rk_serial.2", "uart_frac_div", &clk_uart2_frac_div), + CLK("rk_serial.2", "uart", &clk_uart2), + CLK("rk_serial.2", "pclk_uart", &clk_pclk_uart2), + CLK("rk_serial.3", "uart_div", &clk_uart3_div), + CLK("rk_serial.3", "uart_frac_div", &clk_uart3_frac_div), + CLK("rk_serial.3", "uart", &clk_uart3), + CLK("rk_serial.3", "pclk_uart", &clk_pclk_uart3), CLK1(timer0), CLK1(pclk_timer0), -- 2.34.1