From 2fabcb27761e0f07368f065fda0144d824e1e51c Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Thu, 5 Feb 2009 01:01:16 +0000 Subject: [PATCH] Get rid of 3 non-DebugLoc getNode variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63808 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAG.h | 7 -- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 17 ----- lib/Target/PIC16/PIC16ISelLowering.cpp | 91 +++++++++++++---------- lib/Target/PIC16/PIC16ISelLowering.h | 4 +- lib/Target/XCore/XCoreISelLowering.cpp | 23 +++--- 5 files changed, 65 insertions(+), 77 deletions(-) diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 9d73fb94554..d8f8d39e173 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -449,17 +449,10 @@ public: SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N1, SDValue N2); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N1, SDValue N2); - SDValue getNode(unsigned Opcode, SDVTList VTs, - SDValue N1, SDValue N2, SDValue N3); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N1, SDValue N2, SDValue N3); - SDValue getNode(unsigned Opcode, SDVTList VTs, - SDValue N1, SDValue N2, SDValue N3, SDValue N4); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N1, SDValue N2, SDValue N3, SDValue N4); - SDValue getNode(unsigned Opcode, SDVTList VTs, - SDValue N1, SDValue N2, SDValue N3, SDValue N4, - SDValue N5); SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index cd20643948d..dd00e97b9ef 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3924,23 +3924,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, return getNode(Opcode, DL, VTList, Ops, 2); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - SDValue N1, SDValue N2, SDValue N3) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3) { SDValue Ops[] = { N1, N2, N3 }; return getNode(Opcode, DL, VTList, Ops, 3); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - SDValue N1, SDValue N2, SDValue N3, - SDValue N4) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3, N4); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4) { @@ -3948,12 +3937,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, return getNode(Opcode, DL, VTList, Ops, 4); } -SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, - SDValue N1, SDValue N2, SDValue N3, - SDValue N4, SDValue N5) { - return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3, N4, N5); -} - SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) { diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index 7871a73c7e4..81f08eb90d8 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -631,6 +631,7 @@ SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) { LoadSDNode *LD = dyn_cast(SDValue(N, 0)); SDValue Chain = LD->getChain(); SDValue Ptr = LD->getBasePtr(); + DebugLoc dl = LD->getDebugLoc(); SDValue Load, Offset; SDVTList Tys; @@ -653,7 +654,7 @@ SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) { // Add the pointer offset if any Offset = DAG.getConstant(iter + LoadOffset, MVT::i8); Tys = DAG.getVTList(MVT::i8, MVT::Other); - Load = DAG.getNode(PIC16ISD::PIC16Load, Tys, Chain, PtrLo, PtrHi, + Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi, Offset); PICLoads.push_back(Load); } @@ -675,7 +676,7 @@ SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) { for (iter=0; iter(Op); SDValue Chain = TheCall->getChain(); SDValue Callee = TheCall->getCallee(); + DebugLoc dl = TheCall->getDebugLoc(); unsigned i =0; if (Callee.getValueType() == MVT::i16 && Callee.getOpcode() == ISD::BUILD_PAIR) { @@ -1006,7 +1011,7 @@ SDValue PIC16TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size()); SDValue NewCall = - DAG.getCall(TheCall->getCallingConv(), TheCall->getDebugLoc(), + DAG.getCall(TheCall->getCallingConv(), dl, TheCall->isVarArg(), TheCall->isTailCall(), TheCall->isInreg(), VTs, &Ops[0], Ops.size()); @@ -1061,7 +1066,7 @@ SDValue PIC16TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { OperFlag = getOutFlag(CallArgs); SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); - SDValue PICCall = DAG.getNode(PIC16ISD::CALL, Tys, Chain, Callee, + SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee, OperFlag); Chain = getChain(PICCall); OperFlag = getOutFlag(PICCall); @@ -1108,14 +1113,15 @@ bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp) { } SDValue PIC16TargetLowering:: LowerBinOp(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // We should have handled larger operands in type legalizer itself. assert (Op.getValueType() == MVT::i8 && "illegal Op to lower"); unsigned MemOp = 1; if (NeedToConvertToMemOp(Op, MemOp)) { // Put one value on stack. - SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG); + SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl); - return DAG.getNode(Op.getOpcode(), MVT::i8, Op.getOperand(MemOp ^ 1), + return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1), NewVal); } else { @@ -1126,18 +1132,20 @@ SDValue PIC16TargetLowering:: LowerBinOp(SDValue Op, SelectionDAG &DAG) { SDValue PIC16TargetLowering:: LowerADD(SDValue Op, SelectionDAG &DAG) { // We should have handled larger operands in type legalizer itself. assert (Op.getValueType() == MVT::i8 && "illegal add to lower"); + DebugLoc dl = Op.getDebugLoc(); unsigned MemOp = 1; if (NeedToConvertToMemOp(Op, MemOp)) { // Put one value on stack. - SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG); + SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl); SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag); if (Op.getOpcode() == ISD::ADDE) - return DAG.getNode(Op.getOpcode(), Tys, Op.getOperand(MemOp ^ 1), NewVal, - Op.getOperand(2)); + return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1), + NewVal, Op.getOperand(2)); else - return DAG.getNode(Op.getOpcode(), Tys, Op.getOperand(MemOp ^ 1), NewVal); + return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1), + NewVal); } else if (Op.getOpcode() == ISD::ADD) { return Op; @@ -1148,6 +1156,7 @@ SDValue PIC16TargetLowering:: LowerADD(SDValue Op, SelectionDAG &DAG) { } SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); // We should have handled larger operands in type legalizer itself. assert (Op.getValueType() == MVT::i8 && "illegal sub to lower"); @@ -1157,14 +1166,14 @@ SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) { return SDValue(); // Put first operand on stack. - SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG); + SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl); SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag); if (Op.getOpcode() == ISD::SUBE) - return DAG.getNode(Op.getOpcode(), Tys, NewVal, Op.getOperand(1), + return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1), Op.getOperand(2)); else - return DAG.getNode(Op.getOpcode(), Tys, NewVal, Op.getOperand(1)); + return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1)); } // LowerFORMAL_ARGUMENTS - In Lowering FORMAL ARGUMENTS - MERGE_VALUES nodes @@ -1249,7 +1258,7 @@ static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, // Returns appropriate CMP insn and corresponding condition code in PIC16CC SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned CC, SDValue &PIC16CC, - SelectionDAG &DAG) { + SelectionDAG &DAG, DebugLoc dl) { PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC; // PIC16 sub is literal - W. So Swap the operands and condition if needed. @@ -1294,8 +1303,8 @@ SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS, // These are signed comparisons. SDValue Mask = DAG.getConstant(128, MVT::i8); if (isSignedComparison(CondCode)) { - LHS = DAG.getNode (ISD::XOR, MVT::i8, LHS, Mask); - RHS = DAG.getNode (ISD::XOR, MVT::i8, RHS, Mask); + LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask); + RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask); } SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag); @@ -1305,11 +1314,11 @@ SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS, // for subwf and literal for sublw) and it is used by this operation only. if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS)) && LHS.hasOneUse()) - return DAG.getNode(PIC16ISD::SUBCC, VTs, LHS, RHS); + return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS); // else convert the first operand to mem. - LHS = ConvertToMemOperand (LHS, DAG); - return DAG.getNode(PIC16ISD::SUBCC, VTs, LHS, RHS); + LHS = ConvertToMemOperand (LHS, DAG, dl); + return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS); } @@ -1320,6 +1329,7 @@ SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { SDValue TrueVal = Op.getOperand(2); SDValue FalseVal = Op.getOperand(3); unsigned ORIGCC = ~0; + DebugLoc dl = Op.getDebugLoc(); // If this is a select_cc of a "setcc", and if the setcc got lowered into // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. @@ -1332,9 +1342,9 @@ SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC); SDValue PIC16CC; - SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG); + SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl); - return DAG.getNode (PIC16ISD::SELECT_ICC, TrueVal.getValueType(), TrueVal, + return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal, FalseVal, PIC16CC, Cmp.getValue(1)); } @@ -1400,6 +1410,7 @@ SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { SDValue RHS = Op.getOperand(3); // RHS of the condition. SDValue Dest = Op.getOperand(4); // BB to jump to unsigned ORIGCC = ~0; + DebugLoc dl = Op.getDebugLoc(); // If this is a br_cc of a "setcc", and if the setcc got lowered into // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. @@ -1408,9 +1419,9 @@ SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { // Get the Compare insn and condition code. SDValue PIC16CC; - SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG); + SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl); - return DAG.getNode(PIC16ISD::BRCOND, MVT::Other, Chain, Dest, PIC16CC, + return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC, Cmp.getValue(1)); } diff --git a/lib/Target/PIC16/PIC16ISelLowering.h b/lib/Target/PIC16/PIC16ISelLowering.h index 011d91e4383..22dd22703a4 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.h +++ b/lib/Target/PIC16/PIC16ISelLowering.h @@ -88,7 +88,7 @@ namespace llvm { SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); SDValue getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned OrigCC, SDValue &CC, - SelectionDAG &DAG); + SelectionDAG &DAG, DebugLoc dl); virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB); @@ -146,7 +146,7 @@ namespace llvm { // We can not have both operands of a binary operation in W. // This function is used to put one operand on stack and generate a load. - SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG); + SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG, DebugLoc dl); // This function checks if we need to put an operand of an operation on // stack and generate a load or not. diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index ea9e724b462..cd2d93eee55 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -308,30 +308,31 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DAG) (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && "Unknown operand to lower!"); assert(!Subtarget.isXS1A() && "Cannot custom lower ADD/SUB on xs1a"); + DebugLoc dl = N->getDebugLoc(); // Extract components - SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), - DAG.getConstant(0, MVT::i32)); - SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), - DAG.getConstant(1, MVT::i32)); - SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(1), - DAG.getConstant(0, MVT::i32)); - SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(1), - DAG.getConstant(1, MVT::i32)); + SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + N->getOperand(0), DAG.getConstant(0, MVT::i32)); + SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + N->getOperand(0), DAG.getConstant(1, MVT::i32)); + SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + N->getOperand(1), DAG.getConstant(0, MVT::i32)); + SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + N->getOperand(1), DAG.getConstant(1, MVT::i32)); // Expand unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : XCoreISD::LSUB; SDValue Zero = DAG.getConstant(0, MVT::i32); - SDValue Carry = DAG.getNode(Opcode, DAG.getVTList(MVT::i32, MVT::i32), + SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), LHSL, RHSL, Zero); SDValue Lo(Carry.getNode(), 1); - SDValue Ignored = DAG.getNode(Opcode, DAG.getVTList(MVT::i32, MVT::i32), + SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), LHSH, RHSH, Carry); SDValue Hi(Ignored.getNode(), 1); // Merge the pieces - return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); } SDValue XCoreTargetLowering:: -- 2.34.1