From 30b46d41bcdd48a6b731d84761031347132ed95c Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Sat, 2 Apr 2005 19:04:58 +0000 Subject: [PATCH] FNEG/FABS git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21028 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Alpha/AlphaISelPattern.cpp | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 7242f8f1fdb..a0f3e8e93fe 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -75,10 +75,6 @@ namespace { setOperationAction(ISD::MEMSET , MVT::Other, Expand); setOperationAction(ISD::MEMCPY , MVT::Other, Expand); - // We don't support these yet. - setOperationAction(ISD::FNEG , MVT::f64 , Expand); - setOperationAction(ISD::FABS , MVT::f64 , Expand); - //Doesn't work yet setOperationAction(ISD::SETCC , MVT::f32, Promote); @@ -541,6 +537,23 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result) Node->dump(); assert(0 && "Node not handled!\n"); + case ISD::FNEG: + if(ISD::FABS == N.getOperand(0).getOpcode()) + { + Tmp1 = SelectExpr(N.getOperand(0).getOperand(0)); + BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1); + } else { + Tmp1 = SelectExpr(N.getOperand(0)); + Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS ; + BuildMI(BB, Opc, 2, Result).addReg(Alpha::F31).addReg(Tmp1); + } + return Result; + + case ISD::FABS: + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Tmp1); + return Result; + case ISD::SELECT: { //Tmp1 = SelectExpr(N.getOperand(0)); //Cond -- 2.34.1