From 312eec7ecb712c2e75bd7c40a4460f409c486649 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 1 Feb 2014 08:17:56 +0000 Subject: [PATCH] Simplify some x86 format classes and remove some ambiguities in their application. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200608 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrAVX512.td | 49 ++++++++++++++++--------------- lib/Target/X86/X86InstrFormats.td | 24 +++++++-------- lib/Target/X86/X86InstrSystem.td | 16 +++++----- 3 files changed, 46 insertions(+), 43 deletions(-) diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index 60c953439c8..fefa5fc6bc3 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -850,7 +850,8 @@ multiclass avx512_cmp_packed, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>; + "ps", SSEPackedSingle>, TB, EVEX_4V, EVEX_V512, + EVEX_CD8<32, CD8VF>; defm VCMPPDZ : avx512_cmp_packed, PD, EVEX_4V, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; @@ -1234,14 +1235,14 @@ let Constraints = "$src1 = $dst" in { defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32, "vmovaps", SSEPackedSingle>, - EVEX_V512, EVEX_CD8<32, CD8VF>; + TB, EVEX_V512, EVEX_CD8<32, CD8VF>; defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64, "vmovapd", SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32, "vmovups", SSEPackedSingle>, - EVEX_V512, EVEX_CD8<32, CD8VF>; + TB, EVEX_V512, EVEX_CD8<32, CD8VF>; defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64, "vmovupd", SSEPackedDouble, 0>, PD, EVEX_V512, VEX_W, @@ -1249,7 +1250,7 @@ defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64, def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src), "vmovaps\t{$src, $dst|$dst, $src}", [(alignedstore512 (v16f32 VR512:$src), addr:$dst)], - SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>; + SSEPackedSingle>, EVEX, EVEX_V512, TB, EVEX_CD8<32, CD8VF>; def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src), "vmovapd\t{$src, $dst|$dst, $src}", [(alignedstore512 (v8f64 VR512:$src), addr:$dst)], @@ -1258,7 +1259,7 @@ def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$sr def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src), "vmovups\t{$src, $dst|$dst, $src}", [(store (v16f32 VR512:$src), addr:$dst)], - SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>; + SSEPackedSingle>, EVEX, EVEX_V512, TB, EVEX_CD8<32, CD8VF>; def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src), "vmovupd\t{$src, $dst|$dst, $src}", [(store (v8f64 VR512:$src), addr:$dst)], @@ -1882,13 +1883,13 @@ multiclass avx512_unpack_fp opc, SDNode OpNode, ValueType vt, defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64, VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", - SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>; + SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>; defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64, VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64, VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}", - SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>; + SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>; defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64, VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; @@ -2024,25 +2025,25 @@ multiclass avx512_fp_packed opc, string OpcodeStr, SDNode OpNode, def rr : PI, - EVEX_4V, TB; + EVEX_4V; let mayLoad = 1 in { def rm : PI, EVEX_4V, TB; + itins.rm, d>, EVEX_4V; def rmb : PI, EVEX_4V, EVEX_B, TB; + itins.rm, d>, EVEX_4V, EVEX_B; } } defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem, memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle, - SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>; + SSE_ALU_ITINS_P.s, 1>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>; defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem, memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble, @@ -2051,7 +2052,7 @@ defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem, defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem, memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle, - SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>; + SSE_ALU_ITINS_P.s, 1>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>; defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem, memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble, SSE_ALU_ITINS_P.d, 1>, @@ -2060,11 +2061,11 @@ defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem, defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem, memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle, SSE_ALU_ITINS_P.s, 1>, - EVEX_V512, EVEX_CD8<32, CD8VF>; + EVEX_V512, TB, EVEX_CD8<32, CD8VF>; defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem, memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle, SSE_ALU_ITINS_P.s, 1>, - EVEX_V512, EVEX_CD8<32, CD8VF>; + EVEX_V512, TB, EVEX_CD8<32, CD8VF>; defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem, memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble, @@ -2077,10 +2078,10 @@ defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem, defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem, memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle, - SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>; + SSE_ALU_ITINS_P.s, 0>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>; defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem, memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle, - SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>; + SSE_ALU_ITINS_P.s, 0>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>; defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem, memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble, @@ -2854,7 +2855,8 @@ defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, froun defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend, memopv4f64, f256mem, v8f64, v8f32, - SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>; + SSEPackedDouble>, EVEX_V512, TB, + EVEX_CD8<32, CD8VH>; def : Pat<(v8f64 (extloadv8f32 addr:$src)), (VCVTPS2PDZrm addr:$src)>; @@ -2872,7 +2874,8 @@ def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src), defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp, memopv8i64, i512mem, v16f32, v16i32, - SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>; + SSEPackedSingle>, EVEX_V512, TB, + EVEX_CD8<32, CD8VF>; defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp, memopv4i64, i256mem, v8f64, v8i32, @@ -2891,7 +2894,7 @@ defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint, defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint, memopv16f32, f512mem, v16i32, v16f32, - SSEPackedSingle>, EVEX_V512, + SSEPackedSingle>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>; // cvttps2udq (src, 0, mask-all-ones, sae-current) @@ -2901,7 +2904,7 @@ def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src), defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint, memopv8f64, f512mem, v8i32, v8f64, - SSEPackedDouble>, EVEX_V512, VEX_W, + SSEPackedDouble>, EVEX_V512, TB, VEX_W, EVEX_CD8<64, CD8VF>; // cvttpd2udq (src, 0, mask-all-ones, sae-current) @@ -2971,10 +2974,10 @@ def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src), defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512, memopv16f32, f512mem, SSEPackedSingle>, - EVEX_V512, EVEX_CD8<32, CD8VF>; + TB, EVEX_V512, EVEX_CD8<32, CD8VF>; defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X, memopv8f64, f512mem, SSEPackedDouble>, VEX_W, - EVEX_V512, EVEX_CD8<64, CD8VF>; + TB, EVEX_V512, EVEX_CD8<64, CD8VF>; def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src), (v16i32 immAllZerosV), (i16 -1), imm:$rc)), @@ -3803,7 +3806,7 @@ multiclass avx512_shufp, EVEX_V512, EVEX_CD8<32, CD8VF>; + SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>; defm VSHUFPDZ : avx512_shufp, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index ac04fc4f27a..5ef80bdc315 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -151,7 +151,7 @@ class AdSize { bit hasAdSizePrefix = 1; } class REX_W { bit hasREX_WPrefix = 1; } class LOCK { bit hasLockPrefix = 1; } class REP { bit hasREPPrefix = 1; } -class TB { Prefix OpPrefix = NoPrfx; Map OpMap = TB; } +class TB { Map OpMap = TB; } class D8 { Map OpMap = D8; } class D9 { Map OpMap = D9; } class DA { Map OpMap = DA; } @@ -160,21 +160,21 @@ class DC { Map OpMap = DC; } class DD { Map OpMap = DD; } class DE { Map OpMap = DE; } class DF { Map OpMap = DF; } -class XD { Map OpMap = TB; Prefix OpPrefix = XD; } -class XS { Map OpMap = TB; Prefix OpPrefix = XS; } class T8 { Map OpMap = T8; } class TA { Map OpMap = TA; } class A6 { Map OpMap = A6; } class A7 { Map OpMap = A7; } -class T8XD { Map OpMap = T8; Prefix OpPrefix = XD; } -class T8XS { Map OpMap = T8; Prefix OpPrefix = XS; } -class TAXD { Map OpMap = TA; Prefix OpPrefix = XD; } class XOP8 { Map OpMap = XOP8; } class XOP9 { Map OpMap = XOP9; } class XOPA { Map OpMap = XOPA; } -class PD { Map OpMap = TB; Prefix OpPrefix = PD; } -class T8PD { Map OpMap = T8; Prefix OpPrefix = PD; } -class TAPD { Map OpMap = TA; Prefix OpPrefix = PD; } +class PD : TB { Prefix OpPrefix = PD; } +class XD : TB { Prefix OpPrefix = XD; } +class XS : TB { Prefix OpPrefix = XS; } +class T8PD : T8 { Prefix OpPrefix = PD; } +class T8XD : T8 { Prefix OpPrefix = XD; } +class T8XS : T8 { Prefix OpPrefix = XS; } +class TAPD : TA { Prefix OpPrefix = PD; } +class TAXD : TA { Prefix OpPrefix = XD; } class VEX { bit hasVEXPrefix = 1; } class VEX_W { bit hasVEX_WPrefix = 1; } class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; } @@ -699,7 +699,7 @@ class AVX512AIi8 o, Format F, dag outs, dag ins, string asm, Requires<[HasAVX512]>; class AVX512Ii8 o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TB, + : Ii8, Requires<[HasAVX512]>; class AVX512PDI o, Format F, dag outs, dag ins, string asm, list pattern, InstrItinClass itin = NoItinerary> @@ -711,10 +711,10 @@ class AVX512PSI o, Format F, dag outs, dag ins, string asm, Requires<[HasAVX512]>; class AVX512PIi8 o, Format F, dag outs, dag ins, string asm, list pattern, Domain d, InstrItinClass itin = NoItinerary> - : Ii8, TB, Requires<[HasAVX512]>; + : Ii8, Requires<[HasAVX512]>; class AVX512PI o, Format F, dag outs, dag ins, string asm, list pattern, Domain d, InstrItinClass itin = NoItinerary> - : I, TB, Requires<[HasAVX512]>; + : I, Requires<[HasAVX512]>; class AVX512FMA3 o, Format F, dag outs, dag ins, string asm, listpattern, InstrItinClass itin = NoItinerary> : I, T8PD, diff --git a/lib/Target/X86/X86InstrSystem.td b/lib/Target/X86/X86InstrSystem.td index abed426bce7..4558a1080e0 100644 --- a/lib/Target/X86/X86InstrSystem.td +++ b/lib/Target/X86/X86InstrSystem.td @@ -523,28 +523,28 @@ let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in let Predicates = [HasFSGSBase, In64BitMode] in { def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins), "rdfsbase{l}\t$dst", - [(set GR32:$dst, (int_x86_rdfsbase_32))]>, TB, XS; + [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS; def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins), "rdfsbase{q}\t$dst", - [(set GR64:$dst, (int_x86_rdfsbase_64))]>, TB, XS; + [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS; def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins), "rdgsbase{l}\t$dst", - [(set GR32:$dst, (int_x86_rdgsbase_32))]>, TB, XS; + [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS; def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins), "rdgsbase{q}\t$dst", - [(set GR64:$dst, (int_x86_rdgsbase_64))]>, TB, XS; + [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS; def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src), "wrfsbase{l}\t$src", - [(int_x86_wrfsbase_32 GR32:$src)]>, TB, XS; + [(int_x86_wrfsbase_32 GR32:$src)]>, XS; def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src), "wrfsbase{q}\t$src", - [(int_x86_wrfsbase_64 GR64:$src)]>, TB, XS; + [(int_x86_wrfsbase_64 GR64:$src)]>, XS; def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src), "wrgsbase{l}\t$src", - [(int_x86_wrgsbase_32 GR32:$src)]>, TB, XS; + [(int_x86_wrgsbase_32 GR32:$src)]>, XS; def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src), "wrgsbase{q}\t$src", - [(int_x86_wrgsbase_64 GR64:$src)]>, TB, XS; + [(int_x86_wrgsbase_64 GR64:$src)]>, XS; } //===----------------------------------------------------------------------===// -- 2.34.1