From 325474e06502eb0a593f4ef5a322bab2751f16dc Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 7 Jan 2008 23:56:57 +0000 Subject: [PATCH] Only mark instructions that load a single value without extension as isSimpleLoad = 1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45727 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.cpp | 2 +- lib/Target/ARM/ARMInstrInfo.td | 11 +++++------ lib/Target/ARM/ARMInstrThumb.td | 11 ++++++----- lib/Target/ARM/ARMInstrVFP.td | 2 -- 4 files changed, 12 insertions(+), 14 deletions(-) diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 513f9ecef2e..52d557e819f 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -202,7 +202,7 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); const TargetInstrDesc &TID = MI->getDesc(); unsigned NumOps = TID.getNumOperands(); - bool isLoad = TID.isSimpleLoad(); + bool isLoad = !TID.mayStore(); const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); const MachineOperand &Base = MI->getOperand(2); const MachineOperand &Offset = MI->getOperand(NumOps-3); diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 6b61d86b967..c9b11419f2a 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -684,7 +684,8 @@ def PICADD : AXI1<0x0, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), Pseudo, "$cp:\n\tadd$p $dst, pc, $a", [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; -let isSimpleLoad = 1, AddedComplexity = 10 in { +let AddedComplexity = 10 in { +let isSimpleLoad = 1 in def PICLD : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), Pseudo, "${addr:label}:\n\tldr$p $dst, $addr", [(set GPR:$dst, (load addrmodepc:$addr))]>; @@ -738,7 +739,7 @@ let isReturn = 1, isTerminator = 1 in // FIXME: remove when we have a way to marking a MI with these properties. // FIXME: $dst1 should be a def. But the extra ops must be in the end of the // operand list. -let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in +let isReturn = 1, isTerminator = 1 in def LDM_RET : AXI4<0x0, (outs), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), LdFrm, "ldm${p}${addr:submode} $addr, $dst1", @@ -802,13 +803,13 @@ let isBranch = 1, isTerminator = 1 in { // // Load -let isSimpleLoad = 1 in { +let isSimpleLoad = 1 in def LDR : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, "ldr", " $dst, $addr", [(set GPR:$dst, (load addrmode2:$addr))]>; // Special LDR for loads from non-pc-relative constpools. -let isReMaterializable = 1 in +let isSimpleLoad = 1, isReMaterializable = 1 in def LDRcp : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, "ldr", " $dst, $addr", []>; @@ -875,7 +876,6 @@ def LDRSB_PRE : AI3pr<0xD, (outs GPR:$dst, GPR:$base_wb), def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb), (ins GPR:$base,am3offset:$offset), LdFrm, "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; -} // isSimpleLoad // Store def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm, @@ -939,7 +939,6 @@ def STRB_POST: AI2po<0x1, (outs GPR:$base_wb), // // FIXME: $dst1 should be a def. -let isSimpleLoad = 1 in def LDM : AXI4<0x0, (outs), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), LdFrm, "ldm${p}${addr:submode} $addr, $dst1", diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index c8ed735b64e..8f9bc43c4f6 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -188,7 +188,7 @@ let isReturn = 1, isTerminator = 1 in { } // FIXME: remove when we have a way to marking a MI with these properties. -let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in +let isReturn = 1, isTerminator = 1 in def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins), "pop $dst1", []>; @@ -237,7 +237,7 @@ let isBranch = 1, isTerminator = 1 in // Load Store Instructions. // -let isSimpleLoad = 1 in { +let isSimpleLoad = 1 in def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr), "ldr $dst, $addr", [(set GPR:$dst, (load t_addrmode_s4:$addr))]>; @@ -258,25 +258,27 @@ def tLDRSH : TI2<(outs GPR:$dst), (ins t_addrmode_rr:$addr), "ldrsh $dst, $addr", [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>; +let isSimpleLoad = 1 in def tLDRspi : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr), "ldr $dst, $addr", [(set GPR:$dst, (load t_addrmode_sp:$addr))]>; // Special instruction for restore. It cannot clobber condition register // when it's expanded by eliminateCallFramePseudoInstr(). +let isSimpleLoad = 1 in def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr), "ldr $dst, $addr", []>; // Load tconstpool +let isSimpleLoad = 1 in def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr), "ldr $dst, $addr", [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>; // Special LDR for loads from non-pc-relative constpools. -let isReMaterializable = 1 in +let isSimpleLoad = 1, isReMaterializable = 1 in def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr), "ldr $dst, $addr", []>; -} // isSimpleLoad def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr), "str $src, $addr", @@ -307,7 +309,6 @@ def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr), // TODO: A7-44: LDMIA - load multiple -let isSimpleLoad = 1 in def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins), "pop $dst1", []>; diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 17c6a425ec8..365ca94c6b4 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -110,7 +110,6 @@ def FSTS : ASI5<(outs), (ins SPR:$src, addrmode5:$addr), // Load / store multiple Instructions. // -let isSimpleLoad = 1 in { def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops), "fldm${addr:submode}d${p} ${addr:base}, $dst1", @@ -120,7 +119,6 @@ def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops), "fldm${addr:submode}s${p} ${addr:base}, $dst1", []>; -} // isSimpleLoad let mayStore = 1 in { def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1, -- 2.34.1