From 329944876988b6e2cba7190ff8a75c906ee8fc81 Mon Sep 17 00:00:00 2001
From: Saleem Abdulrasool <compnerd@compnerd.org>
Date: Thu, 18 Dec 2014 16:16:53 +0000
Subject: [PATCH] ARM: fix an off-by-one in the register list access

Fix an off-by-one access introduced in 224502 for push.w and pop.w with single
register operands.  Add test cases for both scenarios.

Thanks to Asiri Rathnayake for pointing out the failure!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224521 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp |  4 ++--
 test/MC/ARM/thumb-load-store-multiple.s   | 18 +++++++++++++-----
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index e9860764962..72b4fda3d07 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -6282,10 +6282,10 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
                    "writeback register not allowed in register list");
 
     if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
-      if (validatetLDMRegList(Inst, Operands, 4))
+      if (validatetLDMRegList(Inst, Operands, 3))
         return true;
     } else {
-      if (validatetSTMRegList(Inst, Operands, 4))
+      if (validatetSTMRegList(Inst, Operands, 3))
         return true;
     }
     break;
diff --git a/test/MC/ARM/thumb-load-store-multiple.s b/test/MC/ARM/thumb-load-store-multiple.s
index e00fc66e8f9..60d2ec3f733 100644
--- a/test/MC/ARM/thumb-load-store-multiple.s
+++ b/test/MC/ARM/thumb-load-store-multiple.s
@@ -1,4 +1,4 @@
-@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null %s 2>&1 \
+@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o - %s 2>&1 \
 @ RUN:     | FileCheck %s
 
 	.syntax unified
@@ -69,10 +69,6 @@ push:
 	.global pop
 	.type pop,%function
 pop:
-	pop {sp}
-@ CHECK-NOT: error: SP may not be in the register list
-	pop {sp, pc}
-@ CHECK-NOT: error: SP may not be in the register list
 	pop {lr, pc}
 @ CHECK: error: PC and LR may not be in the register list simultaneously
 @ CHECK: pop {lr, pc}
@@ -84,3 +80,15 @@ pop:
 @ CHECK: popeq {r1, pc}
 @ CHECK:     ^
 
+	.global valid
+	.type valid,%function
+valid:
+	pop {sp}
+@ CHECK: ldr sp, [sp], #4
+	pop {sp, pc}
+@ CHECK: pop.w {sp, pc}
+	push.w {r0}
+@ CHECK: str r0, [sp, #-4]
+	pop.w {r0}
+@ CHECK: ldr r0, [sp], #4
+
-- 
2.34.1