From 33768dba54ebd6ba4315345316cf426af7a78639 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Fri, 29 Jul 2011 20:02:39 +0000 Subject: [PATCH] ARM CPS mode immediate is 5 bits, not 4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136505 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index b7c245fe1e7..cf4ef65424a 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1319,13 +1319,13 @@ class CPS } let M = 1 in - def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_15:$mode), + def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), "$imod\t$iflags, $mode">; let mode = 0, M = 0 in def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; let imod = 0, iflags = 0, M = 1 in - def CPS1p : CPS<(ins imm0_15:$mode), "\t$mode">; + def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; // Preload signals the memory system of possible future data/instruction access. // These are for disassembly only. -- 2.34.1