From 33977f7b5b63bf1f51ffb8ce2c049e88e21ce334 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Mon, 6 Dec 2010 21:01:55 +0800 Subject: [PATCH] =?utf8?q?rk29:=20clock:=20arm=E9=BB=98=E8=AE=A4=E9=A2=91?= =?utf8?q?=E7=8E=87=E6=94=B9=E4=B8=BA624MHz=EF=BC=8C=E6=9C=89=E4=BA=9B?= =?utf8?q?=E6=9C=BA=E5=99=A8=E6=97=A0=E6=B3=95=E8=B7=91720MHz?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit --- arch/arm/mach-rk29/clock.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-rk29/clock.c b/arch/arm/mach-rk29/clock.c index 202d83a6dac0..19233e70d5e0 100755 --- a/arch/arm/mach-rk29/clock.c +++ b/arch/arm/mach-rk29/clock.c @@ -354,8 +354,9 @@ static const struct arm_pll_set arm_pll[] = { // clk_mhz = 24 * NF / (NR * NO) // mhz NR NF NO adiv hdiv pdiv // ARM_PLL(600, 1, 50, 2, 21, 21, 41), -// ARM_PLL(624, 1, 52, 2, 21, 21, 41), - ARM_PLL(720, 1, 60, 2, 21, 21, 41), + ARM_PLL(624, 1, 52, 2, 21, 21, 41), +// ARM_PLL(720, 1, 60, 2, 21, 21, 41), +// ARM_PLL(1008, 1, 42, 1, 31, 21, 41), // last item, pll power down. ARM_PLL( 24, 1, 64, 8, 21, 21, 41), }; @@ -2109,9 +2110,9 @@ void __init rk29_clock_init(void) rk29_clock_common_init(); - printk(KERN_INFO "Clocking rate (apll/dpll/cpll/ppll/core/aclk/hclk/pclk): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz\n", - arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, periph_pll_clk.rate / MHZ, - clk_core.rate / MHZ, aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ); + printk(KERN_INFO "Clocking rate (apll/dpll/cpll/ppll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz\n", + arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, periph_pll_clk.rate / MHZ, clk_core.rate / MHZ, + aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ); /* * Only enable those clocks we will need, let the drivers -- 2.34.1