From 35c33bd772b3cfb34fdc6b5c9171f955454d0043 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 4 Apr 2010 04:47:45 +0000 Subject: [PATCH] change a ton of code to not implicitly use the "O" raw_ostream member of AsmPrinter. Instead, pass it in explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100306 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/AsmPrinter.h | 3 +- lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 12 +- lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp | 295 +++++++++++------- lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp | 155 +++++---- lib/Target/ARM/AsmPrinter/ARMInstPrinter.h | 117 ++++--- .../Alpha/AsmPrinter/AlphaAsmPrinter.cpp | 23 +- .../AsmPrinter/BlackfinAsmPrinter.cpp | 24 +- .../CellSPU/AsmPrinter/SPUAsmPrinter.cpp | 99 +++--- .../MBlaze/AsmPrinter/MBlazeAsmPrinter.cpp | 127 ++++---- .../MSP430/AsmPrinter/MSP430AsmPrinter.cpp | 2 +- .../MSP430/AsmPrinter/MSP430InstPrinter.cpp | 11 +- .../MSP430/AsmPrinter/MSP430InstPrinter.h | 12 +- lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp | 62 ++-- .../PIC16/AsmPrinter/PIC16AsmPrinter.cpp | 10 +- lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.h | 6 +- .../PowerPC/AsmPrinter/PPCAsmPrinter.cpp | 113 ++++--- .../Sparc/AsmPrinter/SparcAsmPrinter.cpp | 43 +-- .../SystemZ/AsmPrinter/SystemZAsmPrinter.cpp | 37 ++- .../X86/AsmPrinter/X86ATTInstPrinter.cpp | 30 +- lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h | 64 ++-- .../X86/AsmPrinter/X86IntelInstPrinter.cpp | 30 +- .../X86/AsmPrinter/X86IntelInstPrinter.h | 65 ++-- .../XCore/AsmPrinter/XCoreAsmPrinter.cpp | 31 +- utils/TableGen/AsmWriterEmitter.cpp | 2 +- utils/TableGen/AsmWriterInst.cpp | 1 + 25 files changed, 771 insertions(+), 603 deletions(-) diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h index 79c2eb1c928..bcefeff4199 100644 --- a/include/llvm/CodeGen/AsmPrinter.h +++ b/include/llvm/CodeGen/AsmPrinter.h @@ -181,7 +181,8 @@ namespace llvm { /// or other bits of target-specific knowledge into the asmstrings. The /// syntax used is ${:comment}. Targets can override this to add support /// for their own strange codes. - virtual void PrintSpecial(const MachineInstr *MI, const char *Code) const; + virtual void PrintSpecial(const MachineInstr *MI, raw_ostream &OS, + const char *Code) const; /// PrintAsmOperand - Print the specified operand of MI, an INLINEASM /// instruction, using the specified assembler variant. Targets should diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 84128168fe2..870c97e85bd 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -1330,12 +1330,12 @@ void AsmPrinter::EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { /// or other bits of target-specific knowledge into the asmstrings. The /// syntax used is ${:comment}. Targets can override this to add support /// for their own strange codes. -void AsmPrinter::PrintSpecial(const MachineInstr *MI, const char *Code) const { +void AsmPrinter::PrintSpecial(const MachineInstr *MI, raw_ostream &OS, + const char *Code) const { if (!strcmp(Code, "private")) { - O << MAI->getPrivateGlobalPrefix(); + OS << MAI->getPrivateGlobalPrefix(); } else if (!strcmp(Code, "comment")) { - if (VerboseAsm) - O << MAI->getCommentString(); + OS << MAI->getCommentString(); } else if (!strcmp(Code, "uid")) { // Comparing the address of MI isn't sufficient, because machineinstrs may // be allocated to the same address across functions. @@ -1347,7 +1347,7 @@ void AsmPrinter::PrintSpecial(const MachineInstr *MI, const char *Code) const { LastMI = MI; LastFn = ThisF; } - O << Counter; + OS << Counter; } else { std::string msg; raw_string_ostream Msg(msg); @@ -1497,7 +1497,7 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const { } std::string Val(StrStart, StrEnd); - PrintSpecial(MI, Val.c_str()); + PrintSpecial(MI, O, Val.c_str()); LastEmitted = StrEnd+1; break; } diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp index b4aa4a46e1c..486ab00d664 100644 --- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp @@ -87,70 +87,112 @@ namespace { void printInstructionThroughMCStreamer(const MachineInstr *MI); - void printOperand(const MachineInstr *MI, int OpNum, + void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, const char *Modifier = 0); - void printSOImmOperand(const MachineInstr *MI, int OpNum); - void printSOImm2PartOperand(const MachineInstr *MI, int OpNum); - void printSORegOperand(const MachineInstr *MI, int OpNum); - void printAddrMode2Operand(const MachineInstr *MI, int OpNum); - void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum); - void printAddrMode3Operand(const MachineInstr *MI, int OpNum); - void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum); - void printAddrMode4Operand(const MachineInstr *MI, int OpNum, + void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O); + void printSOImm2PartOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printSORegOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode2Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode3Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O, const char *Modifier = 0); - void printAddrMode5Operand(const MachineInstr *MI, int OpNum, + void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O, const char *Modifier = 0); - void printAddrMode6Operand(const MachineInstr *MI, int OpNum); - void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum); + void printAddrMode6Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); void printAddrModePCOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O, const char *Modifier = 0); - void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum); - - void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum); - void printThumbITMask(const MachineInstr *MI, int OpNum); - void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum); + void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum, + raw_ostream &O); + + void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O); + void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O, unsigned Scale); - void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum); - void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum); - void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum); - void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum); - - void printT2SOOperand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum) {} - void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum); - - void printCPSOptionOperand(const MachineInstr *MI, int OpNum) {} - void printMSRMaskOperand(const MachineInstr *MI, int OpNum) {} - void printNegZeroOperand(const MachineInstr *MI, int OpNum) {} - void printPredicateOperand(const MachineInstr *MI, int OpNum); - void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum); - void printSBitModifierOperand(const MachineInstr *MI, int OpNum); - void printPCLabel(const MachineInstr *MI, int OpNum); - void printRegisterList(const MachineInstr *MI, int OpNum); + void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + + void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O); + void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) {} + void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + + void printCPSOptionOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) {} + void printMSRMaskOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) {} + void printNegZeroOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) {} + void printPredicateOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printSBitModifierOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printPCLabel(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printRegisterList(const MachineInstr *MI, int OpNum, + raw_ostream &O); void printCPInstOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O, const char *Modifier); - void printJTBlockOperand(const MachineInstr *MI, int OpNum); - void printJT2BlockOperand(const MachineInstr *MI, int OpNum); - void printTBAddrMode(const MachineInstr *MI, int OpNum); - void printNoHashImmediate(const MachineInstr *MI, int OpNum); - void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum); - void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum); - - void printHex8ImmOperand(const MachineInstr *MI, int OpNum) { + void printJTBlockOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printJT2BlockOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printTBAddrMode(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printNoHashImmediate(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + + void printHex8ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff); } - void printHex16ImmOperand(const MachineInstr *MI, int OpNum) { + void printHex16ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff); } - void printHex32ImmOperand(const MachineInstr *MI, int OpNum) { + void printHex32ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff); } - void printHex64ImmOperand(const MachineInstr *MI, int OpNum) { + void printHex64ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm()); } @@ -160,7 +202,7 @@ namespace { unsigned AsmVariant, const char *ExtraCode); - void printInstruction(const MachineInstr *MI); // autogenerated. + void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen static const char *getRegisterName(unsigned RegNo); virtual void EmitInstruction(const MachineInstr *MI); @@ -265,7 +307,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { } void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { const MachineOperand &MO = MI->getOperand(OpNum); unsigned TF = MO.getTargetFlags(); @@ -344,7 +386,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, } } -static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm, +static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm, const MCAsmInfo *MAI) { // Break it up into two parts that make up a shifter immediate. V = ARM_AM::getSOImmVal(V); @@ -359,8 +401,7 @@ static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm, O << "#" << Imm << ", " << Rot; // Pretty printed version. if (VerboseAsm) { - O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << ' '; + O << "\t" << MAI->getCommentString() << ' '; O << (int)ARM_AM::rotr32(Imm, Rot); } } else { @@ -370,7 +411,8 @@ static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm, /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit /// immediate in bits 0-7. -void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNum); assert(MO.isImm() && "Not a valid so_imm value!"); printSOImm(O, MO.getImm(), VerboseAsm, MAI); @@ -378,18 +420,19 @@ void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) { /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov' /// followed by an 'orr' to materialize. -void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNum); assert(MO.isImm() && "Not a valid so_imm value!"); unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm()); unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm()); printSOImm(O, V1, VerboseAsm, MAI); O << "\n\torr"; - printPredicateOperand(MI, 2); + printPredicateOperand(MI, 2, O); O << "\t"; - printOperand(MI, 0); + printOperand(MI, 0, O); O << ", "; - printOperand(MI, 0); + printOperand(MI, 0, O); O << ", "; printSOImm(O, V2, VerboseAsm, MAI); } @@ -399,7 +442,8 @@ void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) { // REG 0 0 - e.g. R5 // REG REG 0,SH_OPC - e.g. R5, ROR R3 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3 -void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); @@ -419,13 +463,14 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) { } } -void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -451,7 +496,8 @@ void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) { O << "]"; } -void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){ +void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); @@ -473,7 +519,8 @@ void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){ << " #" << ShImm; } -void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); @@ -496,7 +543,8 @@ void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) { O << "]"; } -void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){ +void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op, + raw_ostream &O){ const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); @@ -514,6 +562,7 @@ void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){ } void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op, + raw_ostream &O, const char *Modifier) { const MachineOperand &MO2 = MI->getOperand(Op+1); ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm()); @@ -524,17 +573,18 @@ void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op, if (Mode == ARM_AM::ia) O << ".w"; } else { - printOperand(MI, Op); + printOperand(MI, Op, O); } } void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op, + raw_ostream &O, const char *Modifier) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -560,7 +610,8 @@ void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op, O << "]"; } -void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); @@ -572,7 +623,8 @@ void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) { O << "]"; } -void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op){ +void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op, + raw_ostream &O){ const MachineOperand &MO = MI->getOperand(Op); if (MO.getReg() == 0) O << "!"; @@ -581,9 +633,10 @@ void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op){ } void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op, + raw_ostream &O, const char *Modifier) { if (Modifier && strcmp(Modifier, "label") == 0) { - printPCLabel(MI, Op+1); + printPCLabel(MI, Op+1, O); return; } @@ -593,7 +646,8 @@ void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op, } void -ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) { +ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(Op); uint32_t v = ~MO.getImm(); int32_t lsb = CountTrailingZeros_32(v); @@ -604,12 +658,14 @@ ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) { //===--------------------------------------------------------------------===// -void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op, + raw_ostream &O) { O << "#" << MI->getOperand(Op).getImm() * 4; } void -ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) { +ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op, + raw_ostream &O) { // (3 - the number of trailing zeros) is the number of then / else. unsigned Mask = MI->getOperand(Op).getImm(); unsigned CondBit0 = Mask >> 4 & 1; @@ -625,7 +681,8 @@ ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) { } void -ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) { +ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); O << "[" << getRegisterName(MO1.getReg()); @@ -634,13 +691,14 @@ ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) { void ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op, + raw_ostream &O, unsigned Scale) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -653,19 +711,23 @@ ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op, } void -ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) { - printThumbAddrModeRI5Operand(MI, Op, 1); +ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 1); } void -ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) { - printThumbAddrModeRI5Operand(MI, Op, 2); +ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 2); } void -ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) { - printThumbAddrModeRI5Operand(MI, Op, 4); +ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 4); } -void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) { +void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); O << "[" << getRegisterName(MO1.getReg()); @@ -680,7 +742,8 @@ void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) { // register with shift forms. // REG 0 0 - e.g. R5 // REG IMM, SH_OPC - e.g. R5, LSL #3 -void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); @@ -698,7 +761,8 @@ void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) { } void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); @@ -711,7 +775,8 @@ void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI, } void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); @@ -727,7 +792,8 @@ void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI, } void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); @@ -743,7 +809,8 @@ void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI, } void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); int32_t OffImm = (int32_t)MO1.getImm(); // Don't print +0. @@ -754,7 +821,8 @@ void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, } void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); const MachineOperand &MO3 = MI->getOperand(OpNum+2); @@ -775,19 +843,22 @@ void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI, //===--------------------------------------------------------------------===// -void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); if (CC != ARMCC::AL) O << ARMCondCodeToString(CC); } void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); O << ARMCondCodeToString(CC); } -void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){ +void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O){ unsigned Reg = MI->getOperand(OpNum).getReg(); if (Reg) { assert(Reg == ARM::CPSR && "Expect ARM CPSR register!"); @@ -795,25 +866,27 @@ void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){ } } -void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum, + raw_ostream &O) { int Id = (int)MI->getOperand(OpNum).getImm(); O << MAI->getPrivateGlobalPrefix() << "PC" << getFunctionNumber() << "_" << Id; } -void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "{"; for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { if (MI->getOperand(i).isImplicit()) continue; if ((int)i != OpNum) O << ", "; - printOperand(MI, i); + printOperand(MI, i, O); } O << "}"; } void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { assert(Modifier && "This operand only works with a modifier!"); // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the // data itself. @@ -852,7 +925,8 @@ GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const { return OutContext.GetOrCreateSymbol(Name.str()); } -void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!"); const MachineOperand &MO1 = MI->getOperand(OpNum); @@ -892,7 +966,8 @@ void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) { } } -void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id unsigned JTI = MO1.getIndex(); @@ -933,33 +1008,35 @@ void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) { } } -void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg()); if (MI->getOpcode() == ARM::t2TBH) O << ", lsl #1"; O << ']'; } -void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << MI->getOperand(OpNum).getImm(); } -void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const ConstantFP *FP = MI->getOperand(OpNum).getFPImm(); O << '#' << FP->getValueAPF().convertToFloat(); if (VerboseAsm) { - O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << ' '; + O << "\t\t" << MAI->getCommentString() << ' '; WriteAsOperand(O, FP, /*PrintType=*/false); } } -void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const ConstantFP *FP = MI->getOperand(OpNum).getFPImm(); O << '#' << FP->getValueAPF().convertToDouble(); if (VerboseAsm) { - O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << ' '; + O << "\t\t" << MAI->getCommentString() << ' '; WriteAsOperand(O, FP, /*PrintType=*/false); } } @@ -981,11 +1058,11 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, case 'c': // Don't print "#" before an immediate operand. if (!MI->getOperand(OpNum).isImm()) return true; - printNoHashImmediate(MI, OpNum); + printNoHashImmediate(MI, OpNum, O); return false; case 'P': // Print a VFP double precision register. case 'q': // Print a NEON quad precision register. - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); return false; case 'Q': if (TM.getTargetData()->isLittleEndian()) @@ -1005,7 +1082,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, } } - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); return false; } @@ -1029,7 +1106,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { if (Opc == ARM::CONSTPOOL_ENTRY) EmitAlignment(2); - printInstruction(MI); + printInstruction(MI, O); OutStreamer.AddBlankLine(); } } diff --git a/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp index 30763a9952e..f0fcafbf81f 100644 --- a/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp @@ -107,8 +107,8 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO3 = MI->getOperand(3); O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); - printSBitModifierOperand(MI, 6); - printPredicateOperand(MI, 4); + printSBitModifierOperand(MI, 6, O); + printPredicateOperand(MI, 4, O); O << '\t' << getRegisterName(Dst.getReg()) << ", " << getRegisterName(MO1.getReg()); @@ -133,9 +133,9 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO1 = MI->getOperand(2); if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) { O << '\t' << "push"; - printPredicateOperand(MI, 3); + printPredicateOperand(MI, 3, O); O << '\t'; - printRegisterList(MI, 5); + printRegisterList(MI, 5, O); return; } } @@ -146,9 +146,9 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO1 = MI->getOperand(2); if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) { O << '\t' << "pop"; - printPredicateOperand(MI, 3); + printPredicateOperand(MI, 3, O); O << '\t'; - printRegisterList(MI, 5); + printRegisterList(MI, 5, O); return; } } @@ -159,9 +159,9 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO1 = MI->getOperand(2); if (ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::db) { O << '\t' << "vpush"; - printPredicateOperand(MI, 3); + printPredicateOperand(MI, 3, O); O << '\t'; - printRegisterList(MI, 5); + printRegisterList(MI, 5, O); return; } } @@ -172,18 +172,18 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO1 = MI->getOperand(2); if (ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::ia) { O << '\t' << "vpop"; - printPredicateOperand(MI, 3); + printPredicateOperand(MI, 3, O); O << '\t'; - printRegisterList(MI, 5); + printRegisterList(MI, 5, O); return; } } - printInstruction(MI); + printInstruction(MI, O); } void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { unsigned Reg = Op.getReg(); @@ -247,7 +247,8 @@ static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm, /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit /// immediate in bits 0-7. -void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNum); assert(MO.isImm() && "Not a valid so_imm value!"); printSOImm(O, MO.getImm(), VerboseAsm, &MAI); @@ -255,7 +256,8 @@ void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum) { /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov' /// followed by an 'orr' to materialize. -void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { // FIXME: REMOVE this method. abort(); } @@ -265,7 +267,8 @@ void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum) { // REG 0 0 - e.g. R5 // REG REG 0,SH_OPC - e.g. R5, ROR R3 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3 -void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); const MCOperand &MO3 = MI->getOperand(OpNum+2); @@ -286,13 +289,14 @@ void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum) { } -void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op) { +void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); const MCOperand &MO3 = MI->getOperand(Op+2); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -319,7 +323,8 @@ void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op) { } void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -341,7 +346,8 @@ void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, << " #" << ShImm; } -void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); const MCOperand &MO3 = MI->getOperand(OpNum+2); @@ -362,7 +368,8 @@ void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum) { } void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -381,6 +388,7 @@ void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI, void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O, const char *Modifier) { const MCOperand &MO2 = MI->getOperand(OpNum+1); ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm()); @@ -391,17 +399,18 @@ void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum, if (Mode == ARM_AM::ia) O << ".w"; } else { - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); } } void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O, const char *Modifier) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); return; } @@ -425,7 +434,8 @@ void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, O << "]"; } -void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -438,7 +448,8 @@ void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum) { } void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNum); if (MO.getReg() == 0) O << "!"; @@ -447,12 +458,14 @@ void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI, } void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O, const char *Modifier) { assert(0 && "FIXME: Implement printAddrModePCOperand"); } void ARMInstPrinter::printBitfieldInvMaskImmOperand (const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNum); uint32_t v = ~MO.getImm(); int32_t lsb = CountTrailingZeros_32(v); @@ -461,7 +474,8 @@ void ARMInstPrinter::printBitfieldInvMaskImmOperand (const MCInst *MI, O << '#' << lsb << ", #" << width; } -void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << "{"; for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { if (i != OpNum) O << ", "; @@ -470,7 +484,8 @@ void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum) { O << "}"; } -void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNum); unsigned option = Op.getImm(); unsigned mode = option & 31; @@ -492,7 +507,8 @@ void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum) { O << '#' << mode; } -void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNum); unsigned Mask = Op.getImm(); if (Mask) { @@ -504,7 +520,8 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum) { } } -void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum){ +void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNum); O << '#'; if (Op.getImm() < 0) @@ -513,19 +530,22 @@ void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum){ O << Op.getImm(); } -void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); if (CC != ARMCC::AL) O << ARMCondCodeToString(CC); } void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); O << ARMCondCodeToString(CC); } -void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum){ +void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { if (MI->getOperand(OpNum).getReg()) { assert(MI->getOperand(OpNum).getReg() == ARM::CPSR && "Expect ARM CPSR register!"); @@ -536,26 +556,31 @@ void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum){ void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O, const char *Modifier) { // FIXME: remove this. abort(); } -void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << MI->getOperand(OpNum).getImm(); } -void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { // FIXME: remove this. abort(); } -void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << "#" << MI->getOperand(OpNum).getImm() * 4; } -void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { // (3 - the number of trailing zeros) is the number of then / else. unsigned Mask = MI->getOperand(OpNum).getImm(); unsigned CondBit0 = Mask >> 4 & 1; @@ -570,8 +595,8 @@ void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum) { } } -void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op) -{ +void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); O << "[" << getRegisterName(MO1.getReg()); @@ -579,13 +604,14 @@ void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op) } void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op, + raw_ostream &O, unsigned Scale) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); const MCOperand &MO3 = MI->getOperand(Op+2); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -597,22 +623,23 @@ void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op, O << "]"; } -void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op) -{ - printThumbAddrModeRI5Operand(MI, Op, 1); +void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 1); } -void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op) -{ - printThumbAddrModeRI5Operand(MI, Op, 2); +void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 2); } -void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op) -{ - printThumbAddrModeRI5Operand(MI, Op, 4); +void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 4); } -void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI,unsigned Op) { +void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); O << "[" << getRegisterName(MO1.getReg()); @@ -621,7 +648,8 @@ void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI,unsigned Op) { O << "]"; } -void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg()); if (MI->getOpcode() == ARM::t2TBH) O << ", lsl #1"; @@ -632,7 +660,8 @@ void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum) { // register with shift forms. // REG 0 0 - e.g. R5 // REG IMM, SH_OPC - e.g. R5, LSL #3 -void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -649,7 +678,8 @@ void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum) { } void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -662,7 +692,8 @@ void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -678,7 +709,8 @@ void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -694,7 +726,8 @@ void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); int32_t OffImm = (int32_t)MO1.getImm(); // Don't print +0. @@ -705,7 +738,8 @@ void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); int32_t OffImm = (int32_t)MO1.getImm() / 4; // Don't print +0. @@ -716,7 +750,8 @@ void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); const MCOperand &MO3 = MI->getOperand(OpNum+2); @@ -734,11 +769,13 @@ void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI, O << "]"; } -void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << '#' << MI->getOperand(OpNum).getImm(); } -void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << '#' << MI->getOperand(OpNum).getImm(); } diff --git a/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h b/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h index d41b5dfa6c5..c2b32c1352e 100644 --- a/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h +++ b/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h @@ -28,73 +28,90 @@ public: virtual void printInst(const MCInst *MI); // Autogenerated by tblgen. - void printInstruction(const MCInst *MI); + void printInstruction(const MCInst *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); - void printOperand(const MCInst *MI, unsigned OpNo, + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier = 0); - void printSOImmOperand(const MCInst *MI, unsigned OpNum); - void printSOImm2PartOperand(const MCInst *MI, unsigned OpNum); + void printSOImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printSOImm2PartOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printSORegOperand(const MCInst *MI, unsigned OpNum); - void printAddrMode2Operand(const MCInst *MI, unsigned OpNum); - void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum); - void printAddrMode3Operand(const MCInst *MI, unsigned OpNum); - void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum); - void printAddrMode4Operand(const MCInst *MI, unsigned OpNum, + void printSORegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printAddrMode4Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier = 0); - void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, + void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier = 0); - void printAddrMode6Operand(const MCInst *MI, unsigned OpNum); - void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum); - void printAddrModePCOperand(const MCInst *MI, unsigned OpNum, + void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printAddrModePCOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier = 0); - void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum); + void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); - void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum); - void printThumbITMask(const MCInst *MI, unsigned OpNum); - void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum); + void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); void printThumbAddrModeRI5Operand(const MCInst *MI, unsigned OpNum, - unsigned Scale); - void printThumbAddrModeS1Operand(const MCInst *MI, unsigned OpNum); - void printThumbAddrModeS2Operand(const MCInst *MI, unsigned OpNum); - void printThumbAddrModeS4Operand(const MCInst *MI, unsigned OpNum); - void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum); + raw_ostream &O, unsigned Scale); + void printThumbAddrModeS1Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printThumbAddrModeS2Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printThumbAddrModeS4Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); - void printT2SOOperand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm12Operand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum); + void printT2SOOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printT2AddrModeImm12Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); - void printCPSOptionOperand(const MCInst *MI, unsigned OpNum); - void printMSRMaskOperand(const MCInst *MI, unsigned OpNum); - void printNegZeroOperand(const MCInst *MI, unsigned OpNum); - void printPredicateOperand(const MCInst *MI, unsigned OpNum); - void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum); - void printSBitModifierOperand(const MCInst *MI, unsigned OpNum); - void printRegisterList(const MCInst *MI, unsigned OpNum); - void printCPInstOperand(const MCInst *MI, unsigned OpNum, + void printCPSOptionOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printNegZeroOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printCPInstOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier); - void printJTBlockOperand(const MCInst *MI, unsigned OpNum) {} - void printJT2BlockOperand(const MCInst *MI, unsigned OpNum) {} - void printTBAddrMode(const MCInst *MI, unsigned OpNum); - void printNoHashImmediate(const MCInst *MI, unsigned OpNum); - void printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum); - void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum); - void printHex8ImmOperand(const MCInst *MI, int OpNum) {} - void printHex16ImmOperand(const MCInst *MI, int OpNum) {} - void printHex32ImmOperand(const MCInst *MI, int OpNum) {} - void printHex64ImmOperand(const MCInst *MI, int OpNum) {} + void printJTBlockOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {} + void printJT2BlockOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {} + void printTBAddrMode(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printNoHashImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printHex8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {} + void printHex16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {} + void printHex32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {} + void printHex64ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {} - void printPCLabel(const MCInst *MI, unsigned OpNum); + void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O); // FIXME: Implement. - void PrintSpecial(const MCInst *MI, const char *Kind) {} + void PrintSpecial(const MCInst *MI, raw_ostream &O, const char *Kind) {} }; } diff --git a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp index 093cf052803..6fc9bc13f93 100644 --- a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp +++ b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp @@ -44,16 +44,17 @@ namespace { virtual const char *getPassName() const { return "Alpha Assembly Printer"; } - void printInstruction(const MachineInstr *MI); + void printInstruction(const MachineInstr *MI, raw_ostream &O); void EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); + printInstruction(MI, O); OutStreamer.AddBlankLine(); } static const char *getRegisterName(unsigned RegNo); - void printOp(const MachineOperand &MO, bool IsCallOp = false); - void printOperand(const MachineInstr *MI, int opNum); - void printBaseOffsetPair(const MachineInstr *MI, int i, bool brackets=true); + void printOp(const MachineOperand &MO, raw_ostream &O); + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printBaseOffsetPair(const MachineInstr *MI, int i, raw_ostream &O, + bool brackets=true); virtual void EmitFunctionBodyStart(); virtual void EmitFunctionBodyEnd(); void EmitStartOfAsmFile(Module &M); @@ -69,8 +70,8 @@ namespace { #include "AlphaGenAsmWriter.inc" -void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum) -{ +void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); if (MO.getType() == MachineOperand::MO_Register) { assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && @@ -80,12 +81,12 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum) O << MO.getImm(); assert(MO.getImm() < (1 << 30)); } else { - printOp(MO); + printOp(MO, O); } } -void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { +void AlphaAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) { switch (MO.getType()) { case MachineOperand::MO_Register: O << getRegisterName(MO.getReg()); @@ -148,7 +149,7 @@ void AlphaAsmPrinter::EmitStartOfAsmFile(Module &M) { bool AlphaAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode) { - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } @@ -159,7 +160,7 @@ bool AlphaAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. O << "0("; - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); O << ")"; return false; } diff --git a/lib/Target/Blackfin/AsmPrinter/BlackfinAsmPrinter.cpp b/lib/Target/Blackfin/AsmPrinter/BlackfinAsmPrinter.cpp index a6b48423a52..b206c183b1e 100644 --- a/lib/Target/Blackfin/AsmPrinter/BlackfinAsmPrinter.cpp +++ b/lib/Target/Blackfin/AsmPrinter/BlackfinAsmPrinter.cpp @@ -47,13 +47,13 @@ namespace { return "Blackfin Assembly Printer"; } - void printOperand(const MachineInstr *MI, int opNum); - void printMemoryOperand(const MachineInstr *MI, int opNum); - void printInstruction(const MachineInstr *MI); // autogenerated. + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printMemoryOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printInstruction(const MachineInstr *MI, raw_ostream &O);// autogen'd. static const char *getRegisterName(unsigned RegNo); void EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); + printInstruction(MI, O); OutStreamer.AddBlankLine(); } bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, @@ -69,8 +69,9 @@ extern "C" void LLVMInitializeBlackfinAsmPrinter() { RegisterAsmPrinter X(TheBlackfinTarget); } -void BlackfinAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { - const MachineOperand &MO = MI->getOperand (opNum); +void BlackfinAsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { + const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { case MachineOperand::MO_Register: assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && @@ -105,14 +106,15 @@ void BlackfinAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { } } -void BlackfinAsmPrinter::printMemoryOperand(const MachineInstr *MI, int opNum) { - printOperand(MI, opNum); +void BlackfinAsmPrinter::printMemoryOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { + printOperand(MI, opNum, O); if (MI->getOperand(opNum+1).isImm() && MI->getOperand(opNum+1).getImm() == 0) return; O << " + "; - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); } /// PrintAsmOperand - Print out an operand for an inline asm expression. @@ -131,7 +133,7 @@ bool BlackfinAsmPrinter::PrintAsmOperand(const MachineInstr *MI, } } - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } @@ -144,7 +146,7 @@ bool BlackfinAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, return true; // Unknown modifier O << '['; - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); O << ']'; return false; diff --git a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp index 857ddcf92a5..c2b6f38e33f 100644 --- a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp +++ b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp @@ -52,33 +52,33 @@ namespace { /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. - void printInstruction(const MachineInstr *MI); + void printInstruction(const MachineInstr *MI, raw_ostream &OS); static const char *getRegisterName(unsigned RegNo); void EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); + printInstruction(MI, O); OutStreamer.AddBlankLine(); } - void printOp(const MachineOperand &MO); + void printOp(const MachineOperand &MO, raw_ostream &OS); /// printRegister - Print register according to target requirements. /// - void printRegister(const MachineOperand &MO, bool R0AsZero) { + void printRegister(const MachineOperand &MO, bool R0AsZero, raw_ostream &O){ unsigned RegNo = MO.getReg(); assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); O << getRegisterName(RegNo); } - void printOperand(const MachineInstr *MI, unsigned OpNo) { + void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); if (MO.isReg()) { O << getRegisterName(MO.getReg()); } else if (MO.isImm()) { O << MO.getImm(); } else { - printOp(MO); + printOp(MO, O); } } @@ -89,7 +89,7 @@ namespace { void - printS7ImmOperand(const MachineInstr *MI, unsigned OpNo) + printS7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { int value = MI->getOperand(OpNo).getImm(); value = (value << (32 - 7)) >> (32 - 7); @@ -100,7 +100,7 @@ namespace { } void - printU7ImmOperand(const MachineInstr *MI, unsigned OpNo) + printU7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { unsigned int value = MI->getOperand(OpNo).getImm(); assert(value < (1 << 8) && "Invalid u7 argument"); @@ -108,45 +108,45 @@ namespace { } void - printShufAddr(const MachineInstr *MI, unsigned OpNo) + printShufAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { char value = MI->getOperand(OpNo).getImm(); O << (int) value; O << "("; - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); O << ")"; } void - printS16ImmOperand(const MachineInstr *MI, unsigned OpNo) + printS16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { O << (short) MI->getOperand(OpNo).getImm(); } void - printU16ImmOperand(const MachineInstr *MI, unsigned OpNo) + printU16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { O << (unsigned short)MI->getOperand(OpNo).getImm(); } void - printU32ImmOperand(const MachineInstr *MI, unsigned OpNo) + printU32ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { O << (unsigned)MI->getOperand(OpNo).getImm(); } void - printMemRegReg(const MachineInstr *MI, unsigned OpNo) { + printMemRegReg(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { // When used as the base register, r0 reads constant zero rather than // the value contained in the register. For this reason, the darwin // assembler requires that we print r0 as 0 (no r) when used as the base. const MachineOperand &MO = MI->getOperand(OpNo); O << getRegisterName(MO.getReg()) << ", "; - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); } void - printU18ImmOperand(const MachineInstr *MI, unsigned OpNo) + printU18ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { unsigned int value = MI->getOperand(OpNo).getImm(); assert(value <= (1 << 19) - 1 && "Invalid u18 argument"); @@ -154,7 +154,7 @@ namespace { } void - printS10ImmOperand(const MachineInstr *MI, unsigned OpNo) + printS10ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16) >> 16); @@ -164,7 +164,7 @@ namespace { } void - printU10ImmOperand(const MachineInstr *MI, unsigned OpNo) + printU10ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16) >> 16); @@ -173,7 +173,7 @@ namespace { } void - printDFormAddr(const MachineInstr *MI, unsigned OpNo) + printDFormAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { assert(MI->getOperand(OpNo).isImm() && "printDFormAddr first operand is not immediate"); @@ -182,18 +182,18 @@ namespace { assert((value16 >= -(1 << (9+4)) && value16 <= (1 << (9+4)) - 1) && "Invalid dform s10 offset argument"); O << (value16 & ~0xf) << "("; - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); O << ")"; } void - printAddr256K(const MachineInstr *MI, unsigned OpNo) + printAddr256K(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { /* Note: operand 1 is an offset or symbol name. */ if (MI->getOperand(OpNo).isImm()) { - printS16ImmOperand(MI, OpNo); + printS16ImmOperand(MI, OpNo, O); } else { - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); if (MI->getOperand(OpNo+1).isImm()) { int displ = int(MI->getOperand(OpNo+1).getImm()); if (displ > 0) @@ -204,50 +204,51 @@ namespace { } } - void printCallOperand(const MachineInstr *MI, unsigned OpNo) { - printOp(MI->getOperand(OpNo)); + void printCallOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { + printOp(MI->getOperand(OpNo), O); } - void printPCRelativeOperand(const MachineInstr *MI, unsigned OpNo) { + void printPCRelativeOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { // Used to generate a ".-", but it turns out that the assembler // really wants the target. // // N.B.: This operand is used for call targets. Branch hints are another // animal entirely. - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); } - void printHBROperand(const MachineInstr *MI, unsigned OpNo) { + void printHBROperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { // HBR operands are generated in front of branches, hence, the // program counter plus the target. O << ".+"; - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); } - void printSymbolHi(const MachineInstr *MI, unsigned OpNo) { + void printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { - printS16ImmOperand(MI, OpNo); + printS16ImmOperand(MI, OpNo, O); } else { - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); O << "@h"; } } - void printSymbolLo(const MachineInstr *MI, unsigned OpNo) { + void printSymbolLo(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { - printS16ImmOperand(MI, OpNo); + printS16ImmOperand(MI, OpNo, O); } else { - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); O << "@l"; } } /// Print local store address - void printSymbolLSA(const MachineInstr *MI, unsigned OpNo) { - printOp(MI->getOperand(OpNo)); + void printSymbolLSA(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { + printOp(MI->getOperand(OpNo), O); } - void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo) { + void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { int value = (int) MI->getOperand(OpNo).getImm(); assert((value >= 0 && value < 16) @@ -258,15 +259,13 @@ namespace { } } - void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo) { - if (MI->getOperand(OpNo).isImm()) { - int value = (int) MI->getOperand(OpNo).getImm(); - assert((value >= 0 && value <= 32) - && "Invalid negated immediate rotate 7-bit argument"); - O << -value; - } else { - llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm"); - } + void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O){ + assert(MI->getOperand(OpNo).isImm() && + "Invalid/non-immediate rotate amount in printRotateNeg7Imm"); + int value = (int) MI->getOperand(OpNo).getImm(); + assert((value >= 0 && value <= 32) + && "Invalid negated immediate rotate 7-bit argument"); + O << -value; } }; } // end of anonymous namespace @@ -274,7 +273,7 @@ namespace { // Include the auto-generated portion of the assembly writer #include "SPUGenAsmWriter.inc" -void SPUAsmPrinter::printOp(const MachineOperand &MO) { +void SPUAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) { switch (MO.getType()) { case MachineOperand::MO_Immediate: llvm_report_error("printOp() does not handle immediate values"); @@ -341,7 +340,7 @@ bool SPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, } } - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } @@ -351,7 +350,7 @@ bool SPUAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, const char *ExtraCode) { if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. - printMemRegReg(MI, OpNo); + printMemRegReg(MI, OpNo, O); return false; } diff --git a/lib/Target/MBlaze/AsmPrinter/MBlazeAsmPrinter.cpp b/lib/Target/MBlaze/AsmPrinter/MBlazeAsmPrinter.cpp index ee2c7c8e05f..eec5a61ead1 100644 --- a/lib/Target/MBlaze/AsmPrinter/MBlazeAsmPrinter.cpp +++ b/lib/Target/MBlaze/AsmPrinter/MBlazeAsmPrinter.cpp @@ -64,12 +64,12 @@ namespace { bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode); - void printOperand(const MachineInstr *MI, int opNum); - void printUnsignedImm(const MachineInstr *MI, int opNum); - void printFSLImm(const MachineInstr *MI, int opNum); - void printMemOperand(const MachineInstr *MI, int opNum, + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O); + void printFSLImm(const MachineInstr *MI, int opNum, raw_ostream &O); + void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier = 0); - void printFCCOperand(const MachineInstr *MI, int opNum, + void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier = 0); void printSavedRegsBitmask(); void printHex32(unsigned int Value); @@ -77,17 +77,16 @@ namespace { const char *emitCurrentABIString(); void emitFrameDirective(); - void printInstruction(const MachineInstr *MI); // autogenerated. + void printInstruction(const MachineInstr *MI, raw_ostream &O); void EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); - O << '\n'; + printInstruction(MI, O); + O << '\n'; } virtual void EmitFunctionBodyStart(); virtual void EmitFunctionBodyEnd(); static const char *getRegisterName(unsigned RegNo); virtual void EmitFunctionEntryLabel(); - void EmitStartOfAsmFile(Module &M); }; } // end of anonymous namespace @@ -212,90 +211,92 @@ PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } -void MBlazeAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { +void MBlazeAsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { - case MachineOperand::MO_Register: - O << getRegisterName(MO.getReg()); - break; - - case MachineOperand::MO_Immediate: - O << (int)MO.getImm(); - break; - - case MachineOperand::MO_FPImmediate: { - const ConstantFP* fp = MO.getFPImm(); - printHex32(fp->getValueAPF().bitcastToAPInt().getZExtValue()); - O << ";\t# immediate = " << *fp; - break; - } - - case MachineOperand::MO_MachineBasicBlock: - O << *MO.getMBB()->getSymbol(); - return; - - case MachineOperand::MO_GlobalAddress: - O << *Mang->getSymbol(MO.getGlobal()); - break; - - case MachineOperand::MO_ExternalSymbol: - O << *GetExternalSymbolSymbol(MO.getSymbolName()); - break; - - case MachineOperand::MO_JumpTableIndex: - O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() - << '_' << MO.getIndex(); - break; - - case MachineOperand::MO_ConstantPoolIndex: - O << MAI->getPrivateGlobalPrefix() << "CPI" - << getFunctionNumber() << "_" << MO.getIndex(); - if (MO.getOffset()) - O << "+" << MO.getOffset(); - break; - - default: - llvm_unreachable(""); + case MachineOperand::MO_Register: + O << getRegisterName(MO.getReg()); + break; + + case MachineOperand::MO_Immediate: + O << (int)MO.getImm(); + break; + + case MachineOperand::MO_FPImmediate: { + const ConstantFP* fp = MO.getFPImm(); + printHex32(fp->getValueAPF().bitcastToAPInt().getZExtValue()); + O << ";\t# immediate = " << *fp; + break; + } + + case MachineOperand::MO_MachineBasicBlock: + O << *MO.getMBB()->getSymbol(); + return; + + case MachineOperand::MO_GlobalAddress: + O << *Mang->getSymbol(MO.getGlobal()); + break; + + case MachineOperand::MO_ExternalSymbol: + O << *GetExternalSymbolSymbol(MO.getSymbolName()); + break; + + case MachineOperand::MO_JumpTableIndex: + O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() + << '_' << MO.getIndex(); + break; + + case MachineOperand::MO_ConstantPoolIndex: + O << MAI->getPrivateGlobalPrefix() << "CPI" + << getFunctionNumber() << "_" << MO.getIndex(); + if (MO.getOffset()) + O << "+" << MO.getOffset(); + break; + + default: + llvm_unreachable(""); } } -void MBlazeAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum) { +void MBlazeAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); if (MO.getType() == MachineOperand::MO_Immediate) O << (unsigned int)MO.getImm(); else - printOperand(MI, opNum); + printOperand(MI, opNum, O); } -void MBlazeAsmPrinter::printFSLImm(const MachineInstr *MI, int opNum) { +void MBlazeAsmPrinter::printFSLImm(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); if (MO.getType() == MachineOperand::MO_Immediate) O << "rfsl" << (unsigned int)MO.getImm(); else - printOperand(MI, opNum); + printOperand(MI, opNum, O); } void MBlazeAsmPrinter:: -printMemOperand(const MachineInstr *MI, int opNum, const char *Modifier) { - printOperand(MI, opNum+1); +printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, + const char *Modifier) { + printOperand(MI, opNum+1, O); O << ", "; - printOperand(MI, opNum); + printOperand(MI, opNum, O); } void MBlazeAsmPrinter:: -printFCCOperand(const MachineInstr *MI, int opNum, const char *Modifier) { +printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, + const char *Modifier) { const MachineOperand& MO = MI->getOperand(opNum); O << MBlaze::MBlazeFCCToString((MBlaze::CondCode)MO.getImm()); } -void MBlazeAsmPrinter::EmitStartOfAsmFile(Module &M) { -} - // Force static initialization. extern "C" void LLVMInitializeMBlazeAsmPrinter() { RegisterAsmPrinter X(TheMBlazeTarget); diff --git a/lib/Target/MSP430/AsmPrinter/MSP430AsmPrinter.cpp b/lib/Target/MSP430/AsmPrinter/MSP430AsmPrinter.cpp index 04ac6f1949f..5d5e2e2474c 100644 --- a/lib/Target/MSP430/AsmPrinter/MSP430AsmPrinter.cpp +++ b/lib/Target/MSP430/AsmPrinter/MSP430AsmPrinter.cpp @@ -51,7 +51,7 @@ namespace { } void printMCInst(const MCInst *MI) { - MSP430InstPrinter(O, *MAI).printInstruction(MI); + MSP430InstPrinter(O, *MAI).printInstruction(MI, O); } void printOperand(const MachineInstr *MI, int OpNum, const char* Modifier = 0); diff --git a/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.cpp b/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.cpp index d7636e68a0d..6b99645d23d 100644 --- a/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.cpp +++ b/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.cpp @@ -29,10 +29,11 @@ using namespace llvm; #undef MachineInstr void MSP430InstPrinter::printInst(const MCInst *MI) { - printInstruction(MI); + printInstruction(MI, O); } -void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo) { +void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isImm()) O << Op.getImm(); @@ -43,7 +44,7 @@ void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo) { } void MSP430InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"); const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { @@ -57,6 +58,7 @@ void MSP430InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, } void MSP430InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O, const char *Modifier) { const MCOperand &Base = MI->getOperand(OpNo); const MCOperand &Disp = MI->getOperand(OpNo+1); @@ -84,7 +86,8 @@ void MSP430InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo, O << '(' << getRegisterName(Base.getReg()) << ')'; } -void MSP430InstPrinter::printCCOperand(const MCInst *MI, unsigned OpNo) { +void MSP430InstPrinter::printCCOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { unsigned CC = MI->getOperand(OpNo).getImm(); switch (CC) { diff --git a/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.h b/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.h index 2fac800fcd7..a802cd2bae3 100644 --- a/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.h +++ b/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.h @@ -24,21 +24,21 @@ namespace llvm class MSP430InstPrinter : public MCInstPrinter { public: MSP430InstPrinter(raw_ostream &O, const MCAsmInfo &MAI) : - MCInstPrinter(O, MAI){ + MCInstPrinter(O, MAI) { } virtual void printInst(const MCInst *MI); // Autogenerated by tblgen. - void printInstruction(const MCInst *MI); + void printInstruction(const MCInst *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); - void printOperand(const MCInst *MI, unsigned OpNo, + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier = 0); - void printPCRelImmOperand(const MCInst *MI, unsigned OpNo); - void printSrcMemOperand(const MCInst *MI, unsigned OpNo, + void printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printSrcMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier = 0); - void printCCOperand(const MCInst *MI, unsigned OpNo); + void printCCOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); }; } diff --git a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp index 2a2d9dcaf5a..ce8109d15c5 100644 --- a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp @@ -62,21 +62,21 @@ namespace { bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode); - void printOperand(const MachineInstr *MI, int opNum); - void printUnsignedImm(const MachineInstr *MI, int opNum); - void printMemOperand(const MachineInstr *MI, int opNum, + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O); + void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier = 0); - void printFCCOperand(const MachineInstr *MI, int opNum, + void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier = 0); - void printSavedRegsBitmask(); - void printHex32(unsigned int Value); + void printSavedRegsBitmask(raw_ostream &O); + void printHex32(unsigned int Value, raw_ostream &O); const char *emitCurrentABIString(); - void emitFrameDirective(); + void emitFrameDirective(raw_ostream &O); - void printInstruction(const MachineInstr *MI); // autogenerated. + void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd. void EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); + printInstruction(MI, O); OutStreamer.AddBlankLine(); } virtual void EmitFunctionBodyStart(); @@ -127,7 +127,7 @@ namespace { // Create a bitmask with all callee saved registers for CPU or Floating Point // registers. For CPU registers consider RA, GP and FP for saving if necessary. -void MipsAsmPrinter::printSavedRegsBitmask() { +void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) { const TargetRegisterInfo &RI = *TM.getRegisterInfo(); const MipsFunctionInfo *MipsFI = MF->getInfo(); @@ -156,21 +156,19 @@ void MipsAsmPrinter::printSavedRegsBitmask() { getRegisterNumbering(RI.getRARegister())); // Print CPUBitmask - O << "\t.mask \t"; printHex32(CPUBitmask); O << ',' - << MipsFI->getCPUTopSavedRegOff() << '\n'; + O << "\t.mask \t"; printHex32(CPUBitmask, O); + O << ',' << MipsFI->getCPUTopSavedRegOff() << '\n'; // Print FPUBitmask - O << "\t.fmask\t"; printHex32(FPUBitmask); O << "," + O << "\t.fmask\t"; printHex32(FPUBitmask, O); O << "," << MipsFI->getFPUTopSavedRegOff() << '\n'; } // Print a 32 bit hex number with all numbers. -void MipsAsmPrinter:: -printHex32(unsigned int Value) -{ +void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) { O << "0x"; for (int i = 7; i >= 0; i--) - O << utohexstr( (Value & (0xF << (i*4))) >> (i*4) ); + O << utohexstr((Value & (0xF << (i*4))) >> (i*4)); } //===----------------------------------------------------------------------===// @@ -178,7 +176,7 @@ printHex32(unsigned int Value) //===----------------------------------------------------------------------===// /// Frame Directive -void MipsAsmPrinter::emitFrameDirective() { +void MipsAsmPrinter::emitFrameDirective(raw_ostream &O) { const TargetRegisterInfo &RI = *TM.getRegisterInfo(); unsigned stackReg = RI.getFrameRegister(*MF); @@ -215,8 +213,8 @@ void MipsAsmPrinter::EmitFunctionEntryLabel() { /// EmitFunctionBodyStart - Targets can override this to emit stuff before /// the first basic block in the function. void MipsAsmPrinter::EmitFunctionBodyStart() { - emitFrameDirective(); - printSavedRegsBitmask(); + emitFrameDirective(O); + printSavedRegsBitmask(O); } /// EmitFunctionBodyEnd - Targets can override this to emit stuff after @@ -239,11 +237,12 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } -void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { +void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); bool closeP = false; @@ -307,36 +306,39 @@ void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { if (closeP) O << ")"; } -void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum) { +void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); if (MO.getType() == MachineOperand::MO_Immediate) O << (unsigned short int)MO.getImm(); else - printOperand(MI, opNum); + printOperand(MI, opNum, O); } void MipsAsmPrinter:: -printMemOperand(const MachineInstr *MI, int opNum, const char *Modifier) { +printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, + const char *Modifier) { // when using stack locations for not load/store instructions // print the same way as all normal 3 operand instructions. if (Modifier && !strcmp(Modifier, "stackloc")) { - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); O << ", "; - printOperand(MI, opNum); + printOperand(MI, opNum, O); return; } // Load/Store memory operands -- imm($reg) // If PIC target the target is loaded as the // pattern lw $25,%call16($28) - printOperand(MI, opNum); + printOperand(MI, opNum, O); O << "("; - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); O << ")"; } void MipsAsmPrinter:: -printFCCOperand(const MachineInstr *MI, int opNum, const char *Modifier) { +printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, + const char *Modifier) { const MachineOperand& MO = MI->getOperand(opNum); O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm()); } diff --git a/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.cpp b/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.cpp index 1001d29fd8a..457dd7f9176 100644 --- a/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.cpp +++ b/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.cpp @@ -44,7 +44,7 @@ PIC16AsmPrinter::PIC16AsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, } void PIC16AsmPrinter::EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); + printInstruction(MI, O); OutStreamer.AddBlankLine(); } @@ -156,7 +156,8 @@ bool PIC16AsmPrinter::runOnMachineFunction(MachineFunction &MF) { // printOperand - print operand of insn. -void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) { +void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); const Function *F = MI->getParent()->getParent()->getFunction(); @@ -167,9 +168,7 @@ void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) { std::string RegName = getRegisterName(MO.getReg()); if ((MI->getOpcode() == PIC16::load_indirect) || (MI->getOpcode() == PIC16::store_indirect)) - { RegName.replace (0, 3, "INDF"); - } O << RegName; } return; @@ -216,7 +215,8 @@ void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) { /// printCCOperand - Print the cond code operand. /// -void PIC16AsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) { +void PIC16AsmPrinter::printCCOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { int CC = (int)MI->getOperand(opNum).getImm(); O << PIC16CondCodeToString((PIC16CC::CondCodes)CC); } diff --git a/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.h b/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.h index 8063fcc6fc9..312c54e56fb 100644 --- a/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.h +++ b/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.h @@ -43,9 +43,9 @@ namespace llvm { } bool runOnMachineFunction(MachineFunction &F); - void printOperand(const MachineInstr *MI, int opNum); - void printCCOperand(const MachineInstr *MI, int opNum); - void printInstruction(const MachineInstr *MI); // definition autogenerated. + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printInstruction(const MachineInstr *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); void EmitInstruction(const MachineInstr *MI); diff --git a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp index 7523b6a6171..12c1e53ed7d 100644 --- a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp @@ -92,12 +92,12 @@ namespace { /// from the instruction set description. This method returns true if the /// machine instruction was sufficiently described to print it, otherwise it /// returns false. - void printInstruction(const MachineInstr *MI); + void printInstruction(const MachineInstr *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); virtual void EmitInstruction(const MachineInstr *MI); - void printOp(const MachineOperand &MO); + void printOp(const MachineOperand &MO, raw_ostream &O); /// stripRegisterPrefix - This method strips the character prefix from a /// register name so that only the number is left. Used by for linux asm. @@ -114,7 +114,7 @@ namespace { /// printRegister - Print register according to target requirements. /// - void printRegister(const MachineOperand &MO, bool R0AsZero) { + void printRegister(const MachineOperand &MO, bool R0AsZero, raw_ostream &O){ unsigned RegNo = MO.getReg(); assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); @@ -131,14 +131,14 @@ namespace { O << RegName; } - void printOperand(const MachineInstr *MI, unsigned OpNo) { + void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); if (MO.isReg()) { - printRegister(MO, false); + printRegister(MO, false, O); } else if (MO.isImm()) { O << MO.getImm(); } else { - printOp(MO); + printOp(MO, O); } } @@ -148,49 +148,57 @@ namespace { unsigned AsmVariant, const char *ExtraCode); - void printS5ImmOperand(const MachineInstr *MI, unsigned OpNo) { + void printS5ImmOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { char value = MI->getOperand(OpNo).getImm(); value = (value << (32-5)) >> (32-5); O << (int)value; } - void printU5ImmOperand(const MachineInstr *MI, unsigned OpNo) { + void printU5ImmOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { unsigned char value = MI->getOperand(OpNo).getImm(); assert(value <= 31 && "Invalid u5imm argument!"); O << (unsigned int)value; } - void printU6ImmOperand(const MachineInstr *MI, unsigned OpNo) { + void printU6ImmOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { unsigned char value = MI->getOperand(OpNo).getImm(); assert(value <= 63 && "Invalid u6imm argument!"); O << (unsigned int)value; } - void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo) { + void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { O << (short)MI->getOperand(OpNo).getImm(); } - void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo) { + void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { O << (unsigned short)MI->getOperand(OpNo).getImm(); } - void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo) { + void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { O << (short)(MI->getOperand(OpNo).getImm()*4); } else { O << "lo16("; - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); if (TM.getRelocationModel() == Reloc::PIC_) O << "-\"L" << getFunctionNumber() << "$pb\")"; else O << ')'; } } - void printBranchOperand(const MachineInstr *MI, unsigned OpNo) { + void printBranchOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { // Branches can take an immediate operand. This is used by the branch // selection pass to print $+8, an eight byte displacement from the PC. if (MI->getOperand(OpNo).isImm()) { O << "$+" << MI->getOperand(OpNo).getImm()*4; } else { - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); } } - void printCallOperand(const MachineInstr *MI, unsigned OpNo) { + void printCallOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); if (TM.getRelocationModel() != Reloc::Static) { if (MO.getType() == MachineOperand::MO_GlobalAddress) { @@ -223,21 +231,22 @@ namespace { } } - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); } - void printAbsAddrOperand(const MachineInstr *MI, unsigned OpNo) { + void printAbsAddrOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { O << (int)MI->getOperand(OpNo).getImm()*4; } - void printPICLabel(const MachineInstr *MI, unsigned OpNo) { + void printPICLabel(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { O << "\"L" << getFunctionNumber() << "$pb\"\n"; O << "\"L" << getFunctionNumber() << "$pb\":"; } - void printSymbolHi(const MachineInstr *MI, unsigned OpNo) { + void printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { - printS16ImmOperand(MI, OpNo); + printS16ImmOperand(MI, OpNo, O); } else { if (Subtarget.isDarwin()) O << "ha16("; - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); if (TM.getRelocationModel() == Reloc::PIC_) O << "-\"L" << getFunctionNumber() << "$pb\""; if (Subtarget.isDarwin()) @@ -246,12 +255,12 @@ namespace { O << "@ha"; } } - void printSymbolLo(const MachineInstr *MI, unsigned OpNo) { + void printSymbolLo(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { - printS16ImmOperand(MI, OpNo); + printS16ImmOperand(MI, OpNo, O); } else { if (Subtarget.isDarwin()) O << "lo16("; - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); if (TM.getRelocationModel() == Reloc::PIC_) O << "-\"L" << getFunctionNumber() << "$pb\""; if (Subtarget.isDarwin()) @@ -260,47 +269,49 @@ namespace { O << "@l"; } } - void printcrbitm(const MachineInstr *MI, unsigned OpNo) { + void printcrbitm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { unsigned CCReg = MI->getOperand(OpNo).getReg(); unsigned RegNo = enumRegToMachineReg(CCReg); O << (0x80 >> RegNo); } // The new addressing mode printers. - void printMemRegImm(const MachineInstr *MI, unsigned OpNo) { - printSymbolLo(MI, OpNo); + void printMemRegImm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { + printSymbolLo(MI, OpNo, O); O << '('; if (MI->getOperand(OpNo+1).isReg() && MI->getOperand(OpNo+1).getReg() == PPC::R0) O << "0"; else - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); O << ')'; } - void printMemRegImmShifted(const MachineInstr *MI, unsigned OpNo) { + void printMemRegImmShifted(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) - printS16X4ImmOperand(MI, OpNo); + printS16X4ImmOperand(MI, OpNo, O); else - printSymbolLo(MI, OpNo); + printSymbolLo(MI, OpNo, O); O << '('; if (MI->getOperand(OpNo+1).isReg() && MI->getOperand(OpNo+1).getReg() == PPC::R0) O << "0"; else - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); O << ')'; } - void printMemRegReg(const MachineInstr *MI, unsigned OpNo) { + void printMemRegReg(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { // When used as the base register, r0 reads constant zero rather than // the value contained in the register. For this reason, the darwin // assembler requires that we print r0 as 0 (no r) when used as the base. const MachineOperand &MO = MI->getOperand(OpNo); - printRegister(MO, true); + printRegister(MO, true, O); O << ", "; - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); } - void printTOCEntryLabel(const MachineInstr *MI, unsigned OpNo) { + void printTOCEntryLabel(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); assert(MO.getType() == MachineOperand::MO_GlobalAddress); const MCSymbol *Sym = Mang->getSymbol(MO.getGlobal()); @@ -316,7 +327,7 @@ namespace { } void printPredicateOperand(const MachineInstr *MI, unsigned OpNo, - const char *Modifier); + raw_ostream &O, const char *Modifier); }; /// PPCLinuxAsmPrinter - PowerPC assembly printer, customized for Linux @@ -372,7 +383,7 @@ namespace { // Include the auto-generated portion of the assembly writer #include "PPCGenAsmWriter.inc" -void PPCAsmPrinter::printOp(const MachineOperand &MO) { +void PPCAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) { switch (MO.getType()) { case MachineOperand::MO_Immediate: llvm_unreachable("printOp() does not handle immediate values"); @@ -469,7 +480,7 @@ bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, default: return true; // Unknown modifier. case 'c': // Don't print "$" before a global var name or constant. // PPC never has a prefix. - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; case 'L': // Write second word of DImode reference. // Verify that this operand has two consecutive registers. @@ -488,7 +499,7 @@ bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, } } - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } @@ -503,13 +514,13 @@ bool PPCAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, return true; // Unknown modifier. assert (MI->getOperand(OpNo).isReg()); O << "0("; - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); O << ")"; return false; } void PPCAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo, - const char *Modifier) { + raw_ostream &O, const char *Modifier){ assert(Modifier && "Must specify 'cc' or 'reg' as predicate op modifier!"); unsigned Code = MI->getOperand(OpNo).getImm(); if (!strcmp(Modifier, "cc")) { @@ -530,7 +541,7 @@ void PPCAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo, "Need to specify 'cc' or 'reg' as predicate op modifier!"); // Don't print the register for 'always'. if (Code == PPC::PRED_ALWAYS) return; - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); } } @@ -553,9 +564,9 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { SH = 32-SH; } if (useSubstituteMnemonic) { - printOperand(MI, 0); + printOperand(MI, 0, O); O << ", "; - printOperand(MI, 1); + printOperand(MI, 1, O); O << ", " << (unsigned int)SH; OutStreamer.AddBlankLine(); return; @@ -565,9 +576,9 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { O << "\tmr "; - printOperand(MI, 0); + printOperand(MI, 0, O); O << ", "; - printOperand(MI, 1); + printOperand(MI, 1, O); OutStreamer.AddBlankLine(); return; } @@ -578,16 +589,16 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH if (63-SH == ME) { O << "\tsldi "; - printOperand(MI, 0); + printOperand(MI, 0, O); O << ", "; - printOperand(MI, 1); + printOperand(MI, 1, O); O << ", " << (unsigned int)SH; OutStreamer.AddBlankLine(); return; } } - printInstruction(MI); + printInstruction(MI, O); OutStreamer.AddBlankLine(); } diff --git a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp index 3e40dbb17f8..e854c15714a 100644 --- a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp @@ -38,24 +38,24 @@ namespace { return "Sparc Assembly Printer"; } - void printOperand(const MachineInstr *MI, int opNum); - void printMemOperand(const MachineInstr *MI, int opNum, + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); + void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, const char *Modifier = 0); - void printCCOperand(const MachineInstr *MI, int opNum); + void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); virtual void EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); + printInstruction(MI, O); OutStreamer.AddBlankLine(); } - void printInstruction(const MachineInstr *MI); // autogenerated. + void printInstruction(const MachineInstr *MI, raw_ostream &OS);// autogen'd. static const char *getRegisterName(unsigned RegNo); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode); bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode); - bool printGetPCX(const MachineInstr *MI, unsigned OpNo); + bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS); virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const; @@ -64,7 +64,8 @@ namespace { #include "SparcGenAsmWriter.inc" -void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { +void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand (opNum); bool CloseParen = false; if (MI->getOpcode() == SP::SETHIi && !MO.isReg() && !MO.isImm()) { @@ -103,13 +104,13 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { } void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, - const char *Modifier) { - printOperand(MI, opNum); + raw_ostream &O, const char *Modifier) { + printOperand(MI, opNum, O); // If this is an ADD operand, emit it like normal operands. if (Modifier && !strcmp(Modifier, "arith")) { O << ", "; - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); return; } @@ -124,14 +125,15 @@ void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, if (MI->getOperand(opNum+1).isGlobal() || MI->getOperand(opNum+1).isCPI()) { O << "%lo("; - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); O << ")"; } else { - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); } } -bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum) { +bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum, + raw_ostream &O) { std::string operand = ""; const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { @@ -155,14 +157,15 @@ bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum) { O << ".LLGETPC" << mfNum << '_' << bbNum << ":\n" ; O << "\tor\t" << operand - << ", %lo(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum << ")), " - << operand << '\n'; + << ", %lo(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum + << ")), " << operand << '\n'; O << "\tadd\t" << operand << ", %o7, " << operand << '\n'; return true; } -void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) { +void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { int CC = (int)MI->getOperand(opNum).getImm(); O << SPARCCondCodeToString((SPCC::CondCodes)CC); } @@ -182,7 +185,7 @@ bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, } } - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } @@ -195,7 +198,7 @@ bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, return true; // Unknown modifier O << '['; - printMemOperand(MI, OpNo); + printMemOperand(MI, OpNo, O); O << ']'; return false; diff --git a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp index 349ac3e4b18..77f5b2d00f0 100644 --- a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp +++ b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp @@ -48,21 +48,21 @@ namespace { return "SystemZ Assembly Printer"; } - void printOperand(const MachineInstr *MI, int OpNum, + void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, const char* Modifier = 0); - void printPCRelImmOperand(const MachineInstr *MI, int OpNum); - void printRIAddrOperand(const MachineInstr *MI, int OpNum, + void printPCRelImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O); + void printRIAddrOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, const char* Modifier = 0); - void printRRIAddrOperand(const MachineInstr *MI, int OpNum, + void printRRIAddrOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, const char* Modifier = 0); - void printS16ImmOperand(const MachineInstr *MI, int OpNum) { + void printS16ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) { O << (int16_t)MI->getOperand(OpNum).getImm(); } - void printS32ImmOperand(const MachineInstr *MI, int OpNum) { + void printS32ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) { O << (int32_t)MI->getOperand(OpNum).getImm(); } - void printInstruction(const MachineInstr *MI); // autogenerated. + void printInstruction(const MachineInstr *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); void EmitInstruction(const MachineInstr *MI); @@ -78,11 +78,12 @@ namespace { void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) { // Call the autogenerated instruction printer routines. - printInstruction(MI); + printInstruction(MI, O); OutStreamer.AddBlankLine(); } -void SystemZAsmPrinter::printPCRelImmOperand(const MachineInstr *MI, int OpNum){ +void SystemZAsmPrinter::printPCRelImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNum); switch (MO.getType()) { case MachineOperand::MO_Immediate: @@ -121,7 +122,7 @@ void SystemZAsmPrinter::printPCRelImmOperand(const MachineInstr *MI, int OpNum){ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, - const char* Modifier) { + raw_ostream &O, const char *Modifier) { const MachineOperand &MO = MI->getOperand(OpNum); switch (MO.getType()) { case MachineOperand::MO_Register: { @@ -181,35 +182,37 @@ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, } void SystemZAsmPrinter::printRIAddrOperand(const MachineInstr *MI, int OpNum, - const char* Modifier) { + raw_ostream &O, + const char *Modifier) { const MachineOperand &Base = MI->getOperand(OpNum); // Print displacement operand. - printOperand(MI, OpNum+1); + printOperand(MI, OpNum+1, O); // Print base operand (if any) if (Base.getReg()) { O << '('; - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); O << ')'; } } void SystemZAsmPrinter::printRRIAddrOperand(const MachineInstr *MI, int OpNum, - const char* Modifier) { + raw_ostream &O, + const char *Modifier) { const MachineOperand &Base = MI->getOperand(OpNum); const MachineOperand &Index = MI->getOperand(OpNum+2); // Print displacement operand. - printOperand(MI, OpNum+1); + printOperand(MI, OpNum+1, O); // Print base operand (if any) if (Base.getReg()) { O << '('; - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); if (Index.getReg()) { O << ','; - printOperand(MI, OpNum+2); + printOperand(MI, OpNum+2, O); } O << ')'; } else diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp index 734a545555f..93f3dc1eff0 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp @@ -29,15 +29,18 @@ using namespace llvm; #include "X86GenAsmWriter.inc" #undef MachineInstr -void X86ATTInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); } +void X86ATTInstPrinter::printInst(const MCInst *MI) { + printInstruction(MI, O); +} StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const { return getInstructionName(Opcode); } -void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op) { +void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op, + raw_ostream &O) { switch (MI->getOperand(Op).getImm()) { - default: llvm_unreachable("Invalid ssecc argument!"); + default: assert(0 && "Invalid ssecc argument!"); case 0: O << "eq"; break; case 1: O << "lt"; break; case 2: O << "le"; break; @@ -53,7 +56,8 @@ void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op) { /// being encoded as a pc-relative value (e.g. for jumps and calls). These /// print slightly differently than normal immediates. For example, a $ is not /// emitted. -void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) { +void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isImm()) // Print this as a signed 32-bit value. @@ -64,8 +68,8 @@ void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) { } } -void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo) { - +void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { O << '%' << getRegisterName(Op.getReg()); @@ -81,7 +85,8 @@ void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo) { } } -void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { +void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op, + raw_ostream &O) { const MCOperand &BaseReg = MI->getOperand(Op); const MCOperand &IndexReg = MI->getOperand(Op+2); const MCOperand &DispSpec = MI->getOperand(Op+3); @@ -98,11 +103,11 @@ void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { if (IndexReg.getReg() || BaseReg.getReg()) { O << '('; if (BaseReg.getReg()) - printOperand(MI, Op); + printOperand(MI, Op, O); if (IndexReg.getReg()) { O << ','; - printOperand(MI, Op+2); + printOperand(MI, Op+2, O); unsigned ScaleVal = MI->getOperand(Op+1).getImm(); if (ScaleVal != 1) O << ',' << ScaleVal; @@ -111,11 +116,12 @@ void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { } } -void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op) { +void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op, + raw_ostream &O) { // If this has a segment register, print it. if (MI->getOperand(Op+4).getReg()) { - printOperand(MI, Op+4); + printOperand(MI, Op+4, O); O << ':'; } - printLeaMemReference(MI, Op); + printLeaMemReference(MI, Op, O); } diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h index d109a075b85..3450a057f83 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h +++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h @@ -29,55 +29,55 @@ public: virtual StringRef getOpcodeName(unsigned Opcode) const; // Autogenerated by tblgen. - void printInstruction(const MCInst *MI); + void printInstruction(const MCInst *MI, raw_ostream &OS); static const char *getRegisterName(unsigned RegNo); static const char *getInstructionName(unsigned Opcode); - void printOperand(const MCInst *MI, unsigned OpNo); - void printMemReference(const MCInst *MI, unsigned Op); - void printLeaMemReference(const MCInst *MI, unsigned Op); - void printSSECC(const MCInst *MI, unsigned Op); - void print_pcrel_imm(const MCInst *MI, unsigned OpNo); + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS); + void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS); + void printLeaMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS); + void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &OS); + void print_pcrel_imm(const MCInst *MI, unsigned OpNo, raw_ostream &OS); - void printopaquemem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printi8mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printi16mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printi32mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printi64mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printi128mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printf32mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printf64mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printf80mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printf128mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printlea32mem(const MCInst *MI, unsigned OpNo) { - printLeaMemReference(MI, OpNo); + void printlea32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printLeaMemReference(MI, OpNo, O); } - void printlea64mem(const MCInst *MI, unsigned OpNo) { - printLeaMemReference(MI, OpNo); + void printlea64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printLeaMemReference(MI, OpNo, O); } - void printlea64_32mem(const MCInst *MI, unsigned OpNo) { - printLeaMemReference(MI, OpNo); + void printlea64_32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printLeaMemReference(MI, OpNo, O); } }; diff --git a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp index 610beb550b2..e12b1485730 100644 --- a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp @@ -28,14 +28,17 @@ using namespace llvm; #include "X86GenAsmWriter1.inc" #undef MachineInstr -void X86IntelInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); } +void X86IntelInstPrinter::printInst(const MCInst *MI) { + printInstruction(MI, O); +} StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const { return getInstructionName(Opcode); } -void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op) { +void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op, + raw_ostream &O) { switch (MI->getOperand(Op).getImm()) { - default: llvm_unreachable("Invalid ssecc argument!"); + default: assert(0 && "Invalid ssecc argument!"); case 0: O << "eq"; break; case 1: O << "lt"; break; case 2: O << "le"; break; @@ -49,7 +52,8 @@ void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op) { /// print_pcrel_imm - This is used to print an immediate value that ends up /// being encoded as a pc-relative value. -void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) { +void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isImm()) O << Op.getImm(); @@ -65,9 +69,7 @@ static void PrintRegName(raw_ostream &O, StringRef RegName) { } void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - const char *Modifier) { - assert(Modifier == 0 && "Modifiers should not be used"); - + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { PrintRegName(O, getRegisterName(Op.getReg())); @@ -79,7 +81,8 @@ void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, } } -void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { +void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op, + raw_ostream &O) { const MCOperand &BaseReg = MI->getOperand(Op); unsigned ScaleVal = MI->getOperand(Op+1).getImm(); const MCOperand &IndexReg = MI->getOperand(Op+2); @@ -89,7 +92,7 @@ void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { bool NeedPlus = false; if (BaseReg.getReg()) { - printOperand(MI, Op); + printOperand(MI, Op, O); NeedPlus = true; } @@ -97,7 +100,7 @@ void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { if (NeedPlus) O << " + "; if (ScaleVal != 1) O << ScaleVal << '*'; - printOperand(MI, Op+2); + printOperand(MI, Op+2, O); NeedPlus = true; } @@ -124,11 +127,12 @@ void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { O << ']'; } -void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op) { +void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op, + raw_ostream &O) { // If this has a segment register, print it. if (MI->getOperand(Op+4).getReg()) { - printOperand(MI, Op+4); + printOperand(MI, Op+4, O); O << ':'; } - printLeaMemReference(MI, Op); + printLeaMemReference(MI, Op, O); } diff --git a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h index 545bf84b916..c2d02745110 100644 --- a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h +++ b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h @@ -29,70 +29,69 @@ public: virtual StringRef getOpcodeName(unsigned Opcode) const; // Autogenerated by tblgen. - void printInstruction(const MCInst *MI); + void printInstruction(const MCInst *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); static const char *getInstructionName(unsigned Opcode); - void printOperand(const MCInst *MI, unsigned OpNo, - const char *Modifier = 0); - void printMemReference(const MCInst *MI, unsigned Op); - void printLeaMemReference(const MCInst *MI, unsigned Op); - void printSSECC(const MCInst *MI, unsigned Op); - void print_pcrel_imm(const MCInst *MI, unsigned OpNo); + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O); + void printLeaMemReference(const MCInst *MI, unsigned Op, raw_ostream &O); + void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &O); + void print_pcrel_imm(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printopaquemem(const MCInst *MI, unsigned OpNo) { + void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "OPAQUE PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printi8mem(const MCInst *MI, unsigned OpNo) { + void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "BYTE PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printi16mem(const MCInst *MI, unsigned OpNo) { + void printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "WORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printi32mem(const MCInst *MI, unsigned OpNo) { + void printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "DWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printi64mem(const MCInst *MI, unsigned OpNo) { + void printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "QWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printi128mem(const MCInst *MI, unsigned OpNo) { + void printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "XMMWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printf32mem(const MCInst *MI, unsigned OpNo) { + void printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "DWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printf64mem(const MCInst *MI, unsigned OpNo) { + void printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "QWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printf80mem(const MCInst *MI, unsigned OpNo) { + void printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "XWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printf128mem(const MCInst *MI, unsigned OpNo) { + void printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "XMMWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printlea32mem(const MCInst *MI, unsigned OpNo) { + void printlea32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "DWORD PTR "; - printLeaMemReference(MI, OpNo); + printLeaMemReference(MI, OpNo, O); } - void printlea64mem(const MCInst *MI, unsigned OpNo) { + void printlea64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "QWORD PTR "; - printLeaMemReference(MI, OpNo); + printLeaMemReference(MI, OpNo, O); } - void printlea64_32mem(const MCInst *MI, unsigned OpNo) { + void printlea64_32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "QWORD PTR "; - printLeaMemReference(MI, OpNo); + printLeaMemReference(MI, OpNo, O); } }; diff --git a/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp b/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp index c8823387790..21b6575908c 100644 --- a/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp +++ b/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp @@ -62,13 +62,13 @@ namespace { return "XCore Assembly Printer"; } - void printMemOperand(const MachineInstr *MI, int opNum); - void printInlineJT(const MachineInstr *MI, int opNum, + void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O, const std::string &directive = ".jmptable"); - void printInlineJT32(const MachineInstr *MI, int opNum) { - printInlineJT(MI, opNum, ".jmptable32"); + void printInlineJT32(const MachineInstr *MI, int opNum, raw_ostream &O) { + printInlineJT(MI, opNum, O, ".jmptable32"); } - void printOperand(const MachineInstr *MI, int opNum); + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode); @@ -79,7 +79,7 @@ namespace { void emitFunctionStart(MachineFunction &MF); - void printInstruction(const MachineInstr *MI); // autogenerated. + void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd. static const char *getRegisterName(unsigned RegNo); bool runOnMachineFunction(MachineFunction &MF); @@ -251,21 +251,21 @@ bool XCoreAsmPrinter::runOnMachineFunction(MachineFunction &MF) { return false; } -void XCoreAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) -{ - printOperand(MI, opNum); +void XCoreAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { + printOperand(MI, opNum, O); if (MI->getOperand(opNum+1).isImm() && MI->getOperand(opNum+1).getImm() == 0) return; O << "+"; - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); } void XCoreAsmPrinter:: -printInlineJT(const MachineInstr *MI, int opNum, const std::string &directive) -{ +printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O, + const std::string &directive) { unsigned JTI = MI->getOperand(opNum).getIndex(); const MachineFunction *MF = MI->getParent()->getParent(); const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); @@ -280,7 +280,8 @@ printInlineJT(const MachineInstr *MI, int opNum, const std::string &directive) } } -void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { +void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { case MachineOperand::MO_Register: @@ -319,7 +320,7 @@ void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { bool XCoreAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode) { - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } @@ -332,7 +333,7 @@ void XCoreAsmPrinter::EmitInstruction(const MachineInstr *MI) { OutStreamer.AddBlankLine(); return; } - printInstruction(MI); + printInstruction(MI, O); OutStreamer.AddBlankLine(); } diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index ab1e239a95f..1e95467a3b2 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -248,7 +248,7 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { "/// printInstruction - This method is automatically generated by tablegen\n" "/// from the instruction set description.\n" "void " << Target.getName() << ClassName - << "::printInstruction(const MachineInstr *MI) {\n"; + << "::printInstruction(const MachineInstr *MI, raw_ostream &O) {\n"; std::vector Instructions; diff --git a/utils/TableGen/AsmWriterInst.cpp b/utils/TableGen/AsmWriterInst.cpp index 508e4530d09..b2228b037dd 100644 --- a/utils/TableGen/AsmWriterInst.cpp +++ b/utils/TableGen/AsmWriterInst.cpp @@ -38,6 +38,7 @@ std::string AsmWriterOperand::getCode() const { std::string Result = Str + "(MI"; if (MIOpNo != ~0U) Result += ", " + utostr(MIOpNo); + Result += ", O"; if (!MiModifier.empty()) Result += ", \"" + MiModifier + '"'; return Result + "); "; -- 2.34.1