From 35e7cfb4c095d0ce4303ad030fec6b954c1c5b3a Mon Sep 17 00:00:00 2001 From: Wu Liang feng Date: Wed, 27 Jul 2016 21:57:58 +0800 Subject: [PATCH] arm64: dts: rockchip: add u2phy1_otg node for rk3399 RK3399 SoC USB2 PHY1 comprises with one host-port and one otg-port, now we support PHY1 otg-port. Change-Id: I8e7fd53ce6f1552172044ad2adc3f19e923d1bcd Signed-off-by: Wu Liang feng --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 2d88cf00c4c4..ee2b83effbaf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1222,6 +1222,16 @@ clock-output-names = "clk_usbphy1_480m"; status = "disabled"; + u2phy1_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + u2phy1_host: host-port { #phy-cells = <0>; interrupts = ; -- 2.34.1