From 360ec4c35f279757c079ff295bcc7b8928c18503 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Mon, 13 Jul 2015 20:38:16 +0000 Subject: [PATCH] [Hexagon] Move BitTracker into the llvm namespace and remove redundant qualifications No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242062 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/BitTracker.cpp | 13 ++---- lib/Target/Hexagon/BitTracker.h | 58 +++++++++++------------- lib/Target/Hexagon/HexagonBitTracker.cpp | 9 ++-- lib/Target/Hexagon/HexagonBitTracker.h | 36 +++++++-------- 4 files changed, 52 insertions(+), 64 deletions(-) diff --git a/lib/Target/Hexagon/BitTracker.cpp b/lib/Target/Hexagon/BitTracker.cpp index 1d1996d6b1c..cb7e633fb82 100644 --- a/lib/Target/Hexagon/BitTracker.cpp +++ b/lib/Target/Hexagon/BitTracker.cpp @@ -84,8 +84,7 @@ namespace { } } - -raw_ostream &operator<< (raw_ostream &OS, const BT::BitValue &BV) { +raw_ostream &llvm::operator<<(raw_ostream &OS, const BT::BitValue &BV) { switch (BV.Type) { case BT::BitValue::Top: OS << 'T'; @@ -103,8 +102,7 @@ raw_ostream &operator<< (raw_ostream &OS, const BT::BitValue &BV) { return OS; } - -raw_ostream &operator<< (raw_ostream &OS, const BT::RegisterCell &RC) { +raw_ostream &llvm::operator<<(raw_ostream &OS, const BT::RegisterCell &RC) { unsigned n = RC.Bits.size(); OS << "{ w:" << n; // Instead of printing each bit value individually, try to group them @@ -169,11 +167,8 @@ raw_ostream &operator<< (raw_ostream &OS, const BT::RegisterCell &RC) { return OS; } - -BitTracker::BitTracker(const MachineEvaluator &E, llvm::MachineFunction &F) : - Trace(false), ME(E), MF(F), MRI(F.getRegInfo()), Map(*new CellMapType) { -} - +BitTracker::BitTracker(const MachineEvaluator &E, MachineFunction &F) + : Trace(false), ME(E), MF(F), MRI(F.getRegInfo()), Map(*new CellMapType) {} BitTracker::~BitTracker() { delete ⤅ diff --git a/lib/Target/Hexagon/BitTracker.h b/lib/Target/Hexagon/BitTracker.h index 040a4beb0e1..ed002a794d6 100644 --- a/lib/Target/Hexagon/BitTracker.h +++ b/lib/Target/Hexagon/BitTracker.h @@ -25,7 +25,6 @@ namespace llvm { class MachineInstr; class MachineOperand; class raw_ostream; -} struct BitTracker { struct BitRef; @@ -35,13 +34,13 @@ struct BitTracker { struct RegisterCell; struct MachineEvaluator; - typedef llvm::SetVector BranchTargetList; + typedef SetVector BranchTargetList; struct CellMapType : public std::map { bool has(unsigned Reg) const; }; - BitTracker(const MachineEvaluator &E, llvm::MachineFunction &F); + BitTracker(const MachineEvaluator &E, MachineFunction &F); ~BitTracker(); void run(); @@ -51,18 +50,18 @@ struct BitTracker { RegisterCell get(RegisterRef RR) const; void put(RegisterRef RR, const RegisterCell &RC); void subst(RegisterRef OldRR, RegisterRef NewRR); - bool reached(const llvm::MachineBasicBlock *B) const; + bool reached(const MachineBasicBlock *B) const; private: - void visitPHI(const llvm::MachineInstr *PI); - void visitNonBranch(const llvm::MachineInstr *MI); - void visitBranchesFrom(const llvm::MachineInstr *BI); + void visitPHI(const MachineInstr *PI); + void visitNonBranch(const MachineInstr *MI); + void visitBranchesFrom(const MachineInstr *BI); void visitUsesOf(unsigned Reg); void reset(); typedef std::pair CFGEdge; typedef std::set EdgeSetType; - typedef std::set InstrSetType; + typedef std::set InstrSetType; typedef std::queue EdgeQueueType; EdgeSetType EdgeExec; // Executable flow graph edges. @@ -71,8 +70,8 @@ private: bool Trace; // Enable tracing for debugging. const MachineEvaluator &ME; - llvm::MachineFunction &MF; - llvm::MachineRegisterInfo &MRI; + MachineFunction &MF; + MachineRegisterInfo &MRI; CellMapType ⤅ }; @@ -95,8 +94,8 @@ struct BitTracker::BitRef { struct BitTracker::RegisterRef { RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {} - RegisterRef(const llvm::MachineOperand &MO) - : Reg(MO.getReg()), Sub(MO.getSubReg()) {} + RegisterRef(const MachineOperand &MO) + : Reg(MO.getReg()), Sub(MO.getSubReg()) {} unsigned Reg, Sub; }; @@ -216,8 +215,7 @@ struct BitTracker::BitValue { return Type == One; } - friend llvm::raw_ostream &operator<< (llvm::raw_ostream &OS, - const BitValue &BV); + friend raw_ostream &operator<<(raw_ostream &OS, const BitValue &BV); }; @@ -299,11 +297,10 @@ private: // The DefaultBitN is here only to avoid frequent reallocation of the // memory in the vector. static const unsigned DefaultBitN = 32; - typedef llvm::SmallVector BitValueList; + typedef SmallVector BitValueList; BitValueList Bits; - friend llvm::raw_ostream &operator<< (llvm::raw_ostream &OS, - const RegisterCell &RC); + friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC); }; @@ -352,14 +349,13 @@ inline bool BitTracker::CellMapType::has(unsigned Reg) const { return find(Reg) != end(); } - // A class to evaluate target's instructions and update the cell maps. // This is used internally by the bit tracker. A target that wants to // utilize this should implement the evaluation functions (noted below) // in a subclass of this class. struct BitTracker::MachineEvaluator { - MachineEvaluator(const llvm::TargetRegisterInfo &T, - llvm::MachineRegisterInfo &M) : TRI(T), MRI(M) {} + MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M) + : TRI(T), MRI(M) {} virtual ~MachineEvaluator() {} uint16_t getRegBitWidth(const RegisterRef &RR) const; @@ -382,7 +378,7 @@ struct BitTracker::MachineEvaluator { // Generate cell from an immediate value. RegisterCell eIMM(int64_t V, uint16_t W) const; - RegisterCell eIMM(const llvm::ConstantInt *CI) const; + RegisterCell eIMM(const ConstantInt *CI) const; // Arithmetic. RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const; @@ -431,25 +427,23 @@ struct BitTracker::MachineEvaluator { // does). virtual BitMask mask(unsigned Reg, unsigned Sub) const; // Indicate whether a given register class should be tracked. - virtual bool track(const llvm::TargetRegisterClass *RC) const { - return true; - } + virtual bool track(const TargetRegisterClass *RC) const { return true; } // Evaluate a non-branching machine instruction, given the cell map with // the input values. Place the results in the Outputs map. Return "true" // if evaluation succeeded, "false" otherwise. - virtual bool evaluate(const llvm::MachineInstr *MI, - const CellMapType &Inputs, CellMapType &Outputs) const; + virtual bool evaluate(const MachineInstr *MI, const CellMapType &Inputs, + CellMapType &Outputs) const; // Evaluate a branch, given the cell map with the input values. Fill out // a list of all possible branch targets and indicate (through a flag) // whether the branch could fall-through. Return "true" if this information // has been successfully computed, "false" otherwise. - virtual bool evaluate(const llvm::MachineInstr *BI, - const CellMapType &Inputs, BranchTargetList &Targets, - bool &FallsThru) const = 0; + virtual bool evaluate(const MachineInstr *BI, const CellMapType &Inputs, + BranchTargetList &Targets, bool &FallsThru) const = 0; - const llvm::TargetRegisterInfo &TRI; - llvm::MachineRegisterInfo &MRI; + const TargetRegisterInfo &TRI; + MachineRegisterInfo &MRI; }; -#endif +} // end namespace llvm +#endif diff --git a/lib/Target/Hexagon/HexagonBitTracker.cpp b/lib/Target/Hexagon/HexagonBitTracker.cpp index 8e4baf1d706..021e58a1d08 100644 --- a/lib/Target/Hexagon/HexagonBitTracker.cpp +++ b/lib/Target/Hexagon/HexagonBitTracker.cpp @@ -22,10 +22,11 @@ using namespace llvm; typedef BitTracker BT; -HexagonEvaluator::HexagonEvaluator(const llvm::HexagonRegisterInfo &tri, - llvm::MachineRegisterInfo &mri, const llvm::HexagonInstrInfo &tii, - llvm::MachineFunction &mf) - : MachineEvaluator(tri, mri), MF(mf), MFI(*mf.getFrameInfo()), TII(tii) { +HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri, + MachineRegisterInfo &mri, + const HexagonInstrInfo &tii, + MachineFunction &mf) + : MachineEvaluator(tri, mri), MF(mf), MFI(*mf.getFrameInfo()), TII(tii) { // Populate the VRX map (VR to extension-type). // Go over all the formal parameters of the function. If a given parameter // P is sign- or zero-extended, locate the virtual register holding that diff --git a/lib/Target/Hexagon/HexagonBitTracker.h b/lib/Target/Hexagon/HexagonBitTracker.h index 340c3090044..897af2d7187 100644 --- a/lib/Target/Hexagon/HexagonBitTracker.h +++ b/lib/Target/Hexagon/HexagonBitTracker.h @@ -16,7 +16,6 @@ namespace llvm { class HexagonInstrInfo; class HexagonRegisterInfo; -} struct HexagonEvaluator : public BitTracker::MachineEvaluator { typedef BitTracker::CellMapType CellMapType; @@ -24,27 +23,25 @@ struct HexagonEvaluator : public BitTracker::MachineEvaluator { typedef BitTracker::RegisterCell RegisterCell; typedef BitTracker::BranchTargetList BranchTargetList; - HexagonEvaluator(const llvm::HexagonRegisterInfo &tri, - llvm::MachineRegisterInfo &mri, const llvm::HexagonInstrInfo &tii, - llvm::MachineFunction &mf); + HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri, + const HexagonInstrInfo &tii, MachineFunction &mf); - virtual bool evaluate(const llvm::MachineInstr *MI, - const CellMapType &Inputs, CellMapType &Outputs) const; - virtual bool evaluate(const llvm::MachineInstr *BI, - const CellMapType &Inputs, BranchTargetList &Targets, - bool &FallsThru) const; + bool evaluate(const MachineInstr *MI, const CellMapType &Inputs, + CellMapType &Outputs) const override; + bool evaluate(const MachineInstr *BI, const CellMapType &Inputs, + BranchTargetList &Targets, bool &FallsThru) const override; - virtual BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const; + BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override; - llvm::MachineFunction &MF; - llvm::MachineFrameInfo &MFI; - const llvm::HexagonInstrInfo &TII; + MachineFunction &MF; + MachineFrameInfo &MFI; + const HexagonInstrInfo &TII; private: - bool evaluateLoad(const llvm::MachineInstr *MI, const CellMapType &Inputs, - CellMapType &Outputs) const; - bool evaluateFormalCopy(const llvm::MachineInstr *MI, - const CellMapType &Inputs, CellMapType &Outputs) const; + bool evaluateLoad(const MachineInstr *MI, const CellMapType &Inputs, + CellMapType &Outputs) const; + bool evaluateFormalCopy(const MachineInstr *MI, const CellMapType &Inputs, + CellMapType &Outputs) const; unsigned getNextPhysReg(unsigned PReg, unsigned Width) const; unsigned getVirtRegFor(unsigned PReg) const; @@ -58,9 +55,10 @@ private: ExtType(char t, uint16_t w) : Type(t), Width(w) {} }; // Map VR -> extension type. - typedef llvm::DenseMap RegExtMap; + typedef DenseMap RegExtMap; RegExtMap VRX; }; -#endif +} // end namespace llvm +#endif -- 2.34.1