From 367c3aab790c8a407bb1f97c5f922b69289df89b Mon Sep 17 00:00:00 2001 From: Gary King Date: Wed, 28 Jul 2010 15:03:57 -0700 Subject: [PATCH] [ARM] tegra: fix packet alignment and padding tegra's DMA controller expects to start transfers at word boundaries, and the standard packet alignment (2) was resulting in data corruption also, provide a full cacheline of padding between skbuffs, to eliminate coherency issues between the processor and USB networking devices. Change-Id: Ibb508b512f43c8934d35eb182c8738370b7be585 Signed-off-by: Gary King --- arch/arm/mach-tegra/include/mach/memory.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h index 6151bab62af2..4ebc3e055ed1 100644 --- a/arch/arm/mach-tegra/include/mach/memory.h +++ b/arch/arm/mach-tegra/include/mach/memory.h @@ -24,5 +24,8 @@ /* physical offset of RAM */ #define PHYS_OFFSET UL(0) +#define NET_IP_ALIGN 0 +#define NET_SKB_PAD L1_CACHE_BYTES + #endif -- 2.34.1