From 3779e671ad59ac61dd8750856f606a94cf4c811b Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Fri, 13 May 2016 10:39:40 +0800
Subject: [PATCH] ARM64: dts: rk3399: add pcie support

Change-Id: I3defaf222ddba88fb92c556913c774d466f78456
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 54 ++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index bd5f1326ad72..699a9c832e7f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -991,6 +991,48 @@
 		status = "disabled";
 	};
 
+	pcie0: pcie@f8000000 {
+		compatible = "rockchip,rk3399-pcie";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
+			 <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
+		clock-names = "aclk_pcie", "aclk_perf_pcie",
+			      "hclk_pcie", "clk_pciephy_ref";
+		bus-range = <0x0 0x1>;
+		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
+		ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
+			   0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
+		reg = < 0x0 0xf8000000 0x0 0x2000000 >,
+		      < 0x0 0xfd000000 0x0 0x1000000 >;
+		reg-name = "axi-base", "apb-base";
+		resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
+			 <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
+			 <&cru SRST_PCIE_PIPE>;
+		reset-names = "phy-rst", "core-rst", "mgmt-rst",
+			      "mgmt-sticky-rst", "pipe-rst";
+		rockchip,grf = <&grf>;
+		pcie-conf = <0xe220>;
+		pcie-status = <0xe2a4>;
+		pcie-laneoff = <0xe214>;
+		msi-parent = <&its>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie0 1>,
+				<0 0 0 2 &pcie0 2>,
+				<0 0 0 3 &pcie0 3>,
+				<0 0 0 4 &pcie0 4>;
+		status = "disabled";
+		pcie_intc: interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+		};
+	};
+
 	pwm0: pwm@ff420000 {
 		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 		reg = <0x0 0xff420000 0x0 0x10>;
@@ -2007,5 +2049,17 @@
 					<4 23 RK_FUNC_1 &pcfg_pull_none>;
 			};
 		};
+
+		pcie {
+			pcie_clkreqn: pci-clkreqn {
+				rockchip,pins =
+					<2 26 RK_FUNC_2 &pcfg_pull_none>;
+			};
+
+			pcie_clkreqnb: pci-clkreqnb {
+				rockchip,pins =
+					<4 24 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
 	};
 };
-- 
2.34.1