From 37e9005db3efcd2a635ed0f84e8aee6b421fe007 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Sun, 15 Jan 2006 10:04:45 +0000 Subject: [PATCH] Type inferencing bug git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25337 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/DAGISelEmitter.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index 97f7c155253..2fbc0966f3e 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -544,6 +544,8 @@ static std::vector getIntrinsicType(Record *R, bool NotRegisters, // Pattern fragment types will be resolved when they are inlined. return Unknown; } else if (R->isSubClassOf("Register")) { + if (NotRegisters) + return Unknown; // If the register appears in exactly one regclass, and the regclass has one // value type, use it as the known type. const CodeGenTarget &T = TP.getDAGISelEmitter().getTargetInfo(); -- 2.34.1