From 39890e599f6f0650b06588f4764da1a8c7e6433c Mon Sep 17 00:00:00 2001 From: luowei Date: Fri, 13 Dec 2013 14:52:28 +0800 Subject: [PATCH] improve pinctrl dts format and add rk3188-pinctrl.dtsi file --- arch/arm/boot/dts/rk3188-pinctrl.dtsi | 600 ++++++++++++++++++ arch/arm/boot/dts/rk3188.dtsi | 197 +----- drivers/pinctrl/pinctrl-rockchip.c | 296 ++++++--- include/dt-bindings/pinctrl/rockchip-rk3188.h | 57 +- 4 files changed, 853 insertions(+), 297 deletions(-) create mode 100755 arch/arm/boot/dts/rk3188-pinctrl.dtsi diff --git a/arch/arm/boot/dts/rk3188-pinctrl.dtsi b/arch/arm/boot/dts/rk3188-pinctrl.dtsi new file mode 100755 index 000000000000..3271560a324f --- /dev/null +++ b/arch/arm/boot/dts/rk3188-pinctrl.dtsi @@ -0,0 +1,600 @@ +#include +#include +#include +#include + +/ { + pinctrl@20008000 { + compatible = "rockchip,rk3188-pinctrl"; + reg = <0x20008000 0xa0>, + <0x20008164 0x1a0>; + reg-names = "base", "pull"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@0x2000a000 { + compatible = "rockchip,rk3188-gpio-bank0"; + reg = <0x2000a000 0x100>, + <0x20004064 0x8>; + interrupts = ; + /*clocks = <&clk_gates8 9>;*/ + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@0x2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = ; + /*clocks = <&clk_gates8 10>;*/ + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = ; + /*clocks = <&clk_gates8 11>;*/ + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + /*clocks = <&clk_gates8 12>;*/ + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg_pull_up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg_pull_down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = , + ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + uart0_cts: uart0-cts { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + uart0_rts: uart0-rts { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = , + ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + uart1_cts: uart1-cts { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + uart1_rts: uart1-rts { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = , + ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = , + ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + uart3_cts: uart3-cts { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + uart3_rts: uart3-rts { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + }; + + i2c0 { + i2c0_sda:i2c0-sda { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + i2c0_scl:i2c0-scl { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + }; + + i2c1 { + i2c1_sda:i2c1-sda { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + i2c1_scl:i2c1-scl { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + }; + + i2c2 { + i2c2_sda:i2c2-sda { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + i2c2_scl:i2c2-scl { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + }; + + i2c3 { + i2c3_sda:i2c3-sda { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + i2c3_scl:i2c3-scl { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + }; + + i2c4 { + i2c4_sda:i2c4-sda { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + i2c4_scl:i2c4-scl { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + }; + + spi0 { + spi0_txd:spi0-txd { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + spi0_rxd:spi0-rxd { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + spi0_clk:spi0-clk { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + spi0_cs0:spi0-cs0 { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + spi0_cs1:spi0-cs1 { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + }; + + spi1 { + spi1_txd:spi1-txd { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + spi1_rxd:spi1-rxd { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + spi1_clk:spi1-clk { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + spi1_cs0:spi1-cs0 { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + spi1_cs1:spi1-cs1 { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + }; + + i2s0 { + + i2s0_mclk:i2s0-mclk { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + + }; + + i2s0_sclk:i2s0-sclk { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + + }; + + i2s0_lrckrx:i2s0-lrckrx { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + + }; + + i2s0_lrcktx:i2s0-lrcktx { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + + }; + + i2s0_sdo:i2s0-sdo { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + + }; + + i2s0_sdi:i2s0-sdi { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + + }; + + }; + + + pwm { + pwm0:pwm0 { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + + }; + + + pwm1:pwm1 { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + + pwm2:pwm2 { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + + pwm3:pwm3 { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + }; + + + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + sd0_cmd: sd0-cmd { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + sd0_cd: sd0-cd { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + sd0_wp: sd0-wp { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + sd0_pwr: sd0-pwr { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + sd0_bus1: sd0-bus-width1 { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + sd0_bus4: sd0-bus-width4 { + rockchip,pins = , + , + , + ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + }; + + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + sd1_cmd: sd1-cmd { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + sd1_cd: sd1-cd { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + sd1_wp: sd1-wp { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + sd1_bus1: sd1-bus-width1 { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + + sd1_bus4: sd1-bus-width4 { + rockchip,pins = , + , + , + ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + }; + }; + + + gps { + gps_mag:gps-mag { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + + }; + + gps_sig:gps-sig { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + + }; + + + gps_rfclk:gps-rfclk { + rockchip,pins = ; + rockchip,pull = ; + rockchip,voltage = ; + rockchip,drive = ; + rockchip,tristate = ; + + }; + + }; + + + + //to add + }; +}; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index bea7d7f99554..3f1214b7b6f4 100755 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -1,9 +1,7 @@ -#include -#include -#include -#include #include "skeleton.dtsi" +#include "rk3188-pinctrl.dtsi" + / { compatible = "rockchip,rk3188"; @@ -174,198 +172,7 @@ interrupts = ; }; - pinctrl@20008000 { - compatible = "rockchip,rk3188-pinctrl"; - reg = <0x20008000 0xa0>, - <0x20008164 0x1a0>; - reg-names = "base", "pull"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@0x2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>, - <0x20004064 0x8>; - interrupts = ; - /*clocks = <&clk_gates8 9>;*/ - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@0x2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - /*clocks = <&clk_gates8 10>;*/ - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - /*clocks = <&clk_gates8 11>;*/ - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - /*clocks = <&clk_gates8 12>;*/ - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg_pull_up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg_pull_down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg_pull_none { - bias-disable; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = , - ; - }; - - uart0_cts: uart0-cts { - rockchip,pins = ; - }; - - uart0_rts: uart0-rts { - rockchip,pins = ; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = , - ; - }; - - uart1_cts: uart1-cts { - rockchip,pins = ; - }; - - uart1_rts: uart1-rts { - rockchip,pins = ; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = , - ; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = , - ; - }; - - uart3_cts: uart3-cts { - rockchip,pins = ; - }; - - uart3_rts: uart3-rts { - rockchip,pins = ; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = ; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = ; - }; - - sd0_cd: sd0-cd { - rockchip,pins = ; - }; - - sd0_wp: sd0-wp { - rockchip,pins = ; - }; - - sd0_pwr: sd0-pwr { - rockchip,pins = ; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = ; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = , - , - , - ; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = ; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = ; - }; - - sd1_cd: sd1-cd { - rockchip,pins = ; - }; - - sd1_wp: sd1-wp { - rockchip,pins = ; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = ; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = , - , - , - ; - }; - }; - }; - - uart0: serial@10124000 { compatible = "rockchip,serial"; reg = <0x10124000 0x100>; diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index a93dfe84e18d..b653bee9e8d7 100755 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -41,6 +41,13 @@ #include #include + +#include +#include +#include +#include + + #include "core.h" #include "pinconf.h" @@ -329,9 +336,9 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, /* create config map */ new_map++; for (i = 0; i < grp->npins; i++) { - new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; - new_map[i].data.configs.group_or_pin = - pin_get_name(pctldev, grp->pins[i]); + new_map[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; + new_map[i].data.configs.group_or_pin = grp->name; + //pin_get_name(pctldev, grp->pins[i]); new_map[i].data.configs.configs = grp->data[i].configs; new_map[i].data.configs.num_configs = grp->data[i].nconfigs; } @@ -714,35 +721,46 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, int rc; - param = pinconf_to_config_param(configs); - arg = pinconf_to_config_argument(configs); + param = pinconf_to_config_param(configs); + arg = pinconf_to_config_argument(configs); - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - rc = rockchip_set_pull(bank, pin - bank->pin_base, - param); - if (rc) - return rc; - break; - case PIN_CONFIG_BIAS_PULL_UP: - case PIN_CONFIG_BIAS_PULL_DOWN: - case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: - case PIN_CONFIG_BIAS_BUS_HOLD: - if (!rockchip_pinconf_pull_valid(info->ctrl, param)) - return -ENOTSUPP; + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + rc = rockchip_set_pull(bank, pin - bank->pin_base, + param); + if (rc) + return rc; + break; + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + case PIN_CONFIG_BIAS_BUS_HOLD: + if (!rockchip_pinconf_pull_valid(info->ctrl, param)) + return -ENOTSUPP; - if (!arg) - return -EINVAL; + if (!arg) + return -EINVAL; - rc = rockchip_set_pull(bank, pin - bank->pin_base, - param); - if (rc) - return rc; - break; - default: - return -ENOTSUPP; - break; - } + rc = rockchip_set_pull(bank, pin - bank->pin_base, + param); + if (rc) + return rc; + break; + + case PIN_CONFIG_POWER_SOURCE: + //to do + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + //to do + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + //to do + break; + default: + return -ENOTSUPP; + break; + } DBG_PINCTRL("%s,pin=%d,param=%d\n",__func__,pin, param); @@ -776,20 +794,80 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, *config = 1; break; + + case PIN_CONFIG_POWER_SOURCE: + //to do + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + //to do + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + //to do + break; + default: return -ENOTSUPP; break; } - DBG_PINCTRL("%s:param=%d\n",__func__, param); + DBG_PINCTRL("%s:pin=%d, param=%d\n",__func__, pin, param); + + return 0; +} + +/* set the pin config settings for a specified pin group */ +static int rockchip_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned group, unsigned long config) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins; + unsigned int cnt; + + DBG_PINCTRL("%s:group[%d]:%s\n",__func__, group, info->groups[group].name); + pins = info->groups[group].pins; + + for (cnt = 0; cnt < info->groups[group].npins; cnt++) + rockchip_pinconf_set(pctldev, pins[cnt], config); + + return 0; +} + +/* get the pin config settings for a specified pin group */ +static int rockchip_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long *config) +{ + struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins; + + pins = info->groups[group].pins; + rockchip_pinconf_get(pctldev, pins[0], config); + DBG_PINCTRL("%s:group[%d]:%s\n",__func__, group, info->groups[group].name); return 0; } +static void rockchip_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned pin) +{ + //to do +} + +static void rockchip_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned group) +{ + //to do +} + + static const struct pinconf_ops rockchip_pinconf_ops = { .pin_config_get = rockchip_pinconf_get, .pin_config_set = rockchip_pinconf_set, + .pin_config_group_get = rockchip_pinconf_group_get, + .pin_config_group_set = rockchip_pinconf_group_set, + .pin_config_dbg_show = rockchip_pinconf_dbg_show, + .pin_config_group_dbg_show = rockchip_pinconf_group_dbg_show, }; static const struct of_device_id rockchip_bank_match[] = { @@ -813,82 +891,110 @@ static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, } static int rockchip_pinctrl_parse_groups(struct device_node *np, - struct rockchip_pin_group *grp, - struct rockchip_pinctrl *info, - u32 index) + struct rockchip_pin_group *grp, + struct rockchip_pinctrl *info, + u32 index) { - struct rockchip_pin_bank *bank; - int size; - const __be32 *list; - int num; - int i, j; - int ret; + struct rockchip_pin_bank *bank; + int size; + const __be32 *list; + int i, j; struct union_mode m; + int configlen = 0; + unsigned long *pinconfig; + u32 val; - DBG_PINCTRL("%s:group(%d): %s\n", __func__, index, np->name); - /* Initialise group */ - grp->name = np->name; - - /* - * the binding format is rockchip,pins = , - * do sanity check and calculate pins number - */ - list = of_get_property(np, "rockchip,pins", &size); - /* we do not check return since it's safe node passed down */ - size /= sizeof(*list); - if (!size) { - dev_err(info->dev, "wrong pins number size=%d\n",size); - return -EINVAL; - } - - grp->npins = size / 4; - - grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), - GFP_KERNEL); - grp->data = devm_kzalloc(info->dev, grp->npins * - sizeof(struct rockchip_pin_config), - GFP_KERNEL); - - if (!grp->pins || !grp->data) - return -ENOMEM; - - for (i = 0, j = 0; i < size; i += 4, j++) { - const __be32 *phandle; - struct device_node *np_config; -#if 0 - num = be32_to_cpu(*list++); - bank = bank_num_to_bank(info, num); - if (IS_ERR(bank)) - return PTR_ERR(bank); - - grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); - grp->data[j].func = be32_to_cpu(*list++); -#else + /* Initialise group */ + grp->name = np->name; + + /* + * the binding format is rockchip,pins = , + * do sanity check and calculate pins number + */ + list = of_get_property(np, "rockchip,pins", &size); + /* we do not check return since it's safe node passed down */ + size /= sizeof(*list); + if (!size || size % 1) { + dev_err(info->dev, "wrong pins number or pins and configs should be by 1\n"); + return -EINVAL; + } + + grp->npins = size / 1; + + grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), + GFP_KERNEL); + grp->data = devm_kzalloc(info->dev, grp->npins * + sizeof(struct rockchip_pin_config), + GFP_KERNEL); + if (!grp->pins || !grp->data) + return -ENOMEM; + + pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); + + for (i = 0; i < size; i++) { m.mode = be32_to_cpu(*list++); - + bank = bank_num_to_bank(info, m.mux.bank); if (IS_ERR(bank)) return PTR_ERR(bank); + + grp->pins[i] = bank->pin_base + (m.mux.goff - 0x0A) * 8 + m.mux.off; + grp->data[i].func = m.mode; - grp->pins[j] = bank->pin_base + (m.mux.goff - 0x0A) * 8 + m.mux.off; - grp->data[j].func = m.mode; -#endif - phandle = list++; - if (!phandle) - return -EINVAL; + + j = 0; + configlen = 0; + + if (of_find_property(np, "rockchip,pull", NULL)) + configlen++; + if (of_find_property(np, "rockchip,voltage", NULL)) + configlen++; + if (of_find_property(np, "rockchip,drive", NULL)) + configlen++; + if (of_find_property(np, "rockchip,tristate", NULL)) + configlen++; + + pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); + + if (!of_property_read_u32(np, "allwinner,pull", &val)) { + enum pin_config_param pull = PIN_CONFIG_END; + if (val == 1) + pull = PIN_CONFIG_BIAS_PULL_UP; + else if (val == 2) + pull = PIN_CONFIG_BIAS_PULL_DOWN; + + pinconfig[j++] = pinconf_to_config_packed(pull, 0); + } - np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); - ret = pinconf_generic_parse_dt_config(np_config, - &grp->data[j].configs, &grp->data[j].nconfigs); - if (ret) - return ret; - } + if (!of_property_read_u32(np, "rockchip,voltage", &val)) { + pinconfig[j++] = + pinconf_to_config_packed(PIN_CONFIG_POWER_SOURCE, + val); + } - return 0; + if (!of_property_read_u32(np, "rockchip,drive", &val)) { + pinconfig[j++] = + pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, + val); + } + + if (!of_property_read_u32(np, "rockchip,tristate", &val)) { + pinconfig[j++] = + pinconf_to_config_packed(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, + val); + } + + grp->data[i].configs = pinconfig; + grp->data[i].nconfigs = configlen; + + } + + return 0; } + static int rockchip_pinctrl_parse_functions(struct device_node *np, struct rockchip_pinctrl *info, u32 index) @@ -1582,7 +1688,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev, { struct rockchip_pin_ctrl *ctrl = info->ctrl; struct rockchip_pin_bank *bank = ctrl->pin_banks; - unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + //unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; int i; for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { @@ -1773,13 +1879,13 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( return ctrl; } - +#if 0 static irqreturn_t pinctrl_interrupt_test(int irq, void *dev_id) { printk("%s:line=%d\n",__func__, __LINE__); return IRQ_HANDLED; } - +#endif static int rockchip_pinctrl_probe(struct platform_device *pdev) { struct rockchip_pinctrl *info; diff --git a/include/dt-bindings/pinctrl/rockchip-rk3188.h b/include/dt-bindings/pinctrl/rockchip-rk3188.h index 95a2ff55aaa7..d4207d9c7537 100755 --- a/include/dt-bindings/pinctrl/rockchip-rk3188.h +++ b/include/dt-bindings/pinctrl/rockchip-rk3188.h @@ -451,14 +451,57 @@ #define JTAG_TMS 0x3d62 #define HOST_DRV_VBUS 0x3d63 +/*warning:don not chang the following value*/ +#define VALUE_PULL_DISABLE 0 +#define VALUE_PULL_UP 1 +#define VALUE_PULL_DOWN 2 +#define VALUE_PULL_DEFAULT 3 -#define VOL_DOMAIN_DEFAULT 0 -#define VOL_DOMAIN_10V 1 -#define VOL_DOMAIN_12V 2 -#define VOL_DOMAIN_18V 3 -#define VOL_DOMAIN_30V 4 -#define VOL_DOMAIN_33V 5 -#define VOL_DOMAIN_50V 6 +#define VALUE_VOL_DEFAULT 0 +#define VALUE_VOL_33V 0 +#define VALUE_VOL_18V 1 + +#define VALUE_DRV_DEFAULT 0 +#define VALUE_DRV_2MA 0 +#define VALUE_DRV_4MA 1 +#define VALUE_DRV_8MA 2 +#define VALUE_DRV_12MA 3 + +#define VALUE_TRI_DEFAULT 0 +#define VALUE_TRI_FALSE 0 +#define VALUE_TRI_TRUE 1 + + +/* + * pin config bit field definitions + * + * pull-up: 1..0 (2) + * voltage: 3..2 (2) + * drive: 5..4 (2) + * trisiate: 7..6 (2) + * + * MSB of each field is presence bit for the config. + */ +#define PULL_SHIFT 0 +#define PULL_PRESENT (1 << 2) +#define VOL_SHIFT 3 +#define VOL_PRESENT (1 << 5) +#define DRV_SHIFT 6 +#define DRV_PRESENT (1 << 8) +#define TRI_SHIFT 9 +#define TRI_PRESENT (1 << 11) + +#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x3) +#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x3) +#define CONFIG_TO_DRV(c) ((c) >> DRV_SHIFT & 0x3) +#define CONFIG_TO_TRI(c) ((c) >> TRI_SHIFT & 0x3) + + +#define MAX_NUM_CONFIGS 4 +#define POS_PULL 0 +#define POS_VOL 1 +#define POS_DRV 2 +#define POS_TRI 3 //#define rk29_mux_api_set(name, mode) iomux_set(mode) -- 2.34.1