From 39b5c0c049a19c7a7feffc9506da07923cc136e4 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Thu, 29 Nov 2012 03:34:17 +0000 Subject: [PATCH] Use MCPhysReg for RegisterClassInfo allocation orders. This saves a bit of memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168852 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/RegisterClassInfo.h | 6 +++--- lib/CodeGen/AggressiveAntiDepBreaker.cpp | 2 +- lib/CodeGen/AllocationOrder.cpp | 6 +++--- lib/CodeGen/AllocationOrder.h | 8 +++++--- lib/CodeGen/CriticalAntiDepBreaker.cpp | 2 +- lib/CodeGen/RegAllocFast.cpp | 6 +++--- lib/CodeGen/RegisterClassInfo.cpp | 8 ++++---- 7 files changed, 20 insertions(+), 18 deletions(-) diff --git a/include/llvm/CodeGen/RegisterClassInfo.h b/include/llvm/CodeGen/RegisterClassInfo.h index 4467b62f237..12bd1c61d25 100644 --- a/include/llvm/CodeGen/RegisterClassInfo.h +++ b/include/llvm/CodeGen/RegisterClassInfo.h @@ -29,10 +29,10 @@ class RegisterClassInfo { unsigned Tag; unsigned NumRegs; bool ProperSubClass; - OwningArrayPtr Order; + OwningArrayPtr Order; RCInfo() : Tag(0), NumRegs(0), ProperSubClass(false) {} - operator ArrayRef() const { + operator ArrayRef() const { return makeArrayRef(Order.get(), NumRegs); } }; @@ -84,7 +84,7 @@ public: /// getOrder - Returns the preferred allocation order for RC. The order /// contains no reserved registers, and registers that alias callee saved /// registers come last. - ArrayRef getOrder(const TargetRegisterClass *RC) const { + ArrayRef getOrder(const TargetRegisterClass *RC) const { return get(RC); } diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/lib/CodeGen/AggressiveAntiDepBreaker.cpp index 7a1c049d522..880a78fb5e1 100644 --- a/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -616,7 +616,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( const TargetRegisterClass *SuperRC = TRI->getMinimalPhysRegClass(SuperReg, MVT::Other); - ArrayRef Order = RegClassInfo.getOrder(SuperRC); + ArrayRef Order = RegClassInfo.getOrder(SuperRC); if (Order.empty()) { DEBUG(dbgs() << "\tEmpty Super Regclass!!\n"); return false; diff --git a/lib/CodeGen/AllocationOrder.cpp b/lib/CodeGen/AllocationOrder.cpp index 96c907aa9c4..bad4912e722 100644 --- a/lib/CodeGen/AllocationOrder.cpp +++ b/lib/CodeGen/AllocationOrder.cpp @@ -42,7 +42,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg, if (HintPair.first) { const TargetRegisterInfo &TRI = VRM.getTargetRegInfo(); // The remaining allocation order may depend on the hint. - ArrayRef Order = + ArrayRef Order = TRI.getRawAllocationOrder(RC, HintPair.first, Hint, VRM.getMachineFunction()); if (Order.empty()) @@ -50,7 +50,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg, // Copy the allocation order with reserved registers removed. OwnedBegin = true; - unsigned *P = new unsigned[Order.size()]; + MCPhysReg *P = new MCPhysReg[Order.size()]; Begin = P; for (unsigned i = 0; i != Order.size(); ++i) if (!MRI.isReserved(Order[i])) @@ -63,7 +63,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg, } else { // If there is no hint or just a normal hint, use the cached allocation // order from RegisterClassInfo. - ArrayRef O = RCI.getOrder(RC); + ArrayRef O = RCI.getOrder(RC); Begin = O.begin(); End = O.end(); } diff --git a/lib/CodeGen/AllocationOrder.h b/lib/CodeGen/AllocationOrder.h index 0ce7e0c3b5f..862a3ee1923 100644 --- a/lib/CodeGen/AllocationOrder.h +++ b/lib/CodeGen/AllocationOrder.h @@ -17,15 +17,17 @@ #ifndef LLVM_CODEGEN_ALLOCATIONORDER_H #define LLVM_CODEGEN_ALLOCATIONORDER_H +#include "llvm/MC/MCRegisterInfo.h" + namespace llvm { class RegisterClassInfo; class VirtRegMap; class AllocationOrder { - const unsigned *Begin; - const unsigned *End; - const unsigned *Pos; + const MCPhysReg *Begin; + const MCPhysReg *End; + const MCPhysReg *Pos; const RegisterClassInfo &RCI; unsigned Hint; bool OwnedBegin; diff --git a/lib/CodeGen/CriticalAntiDepBreaker.cpp b/lib/CodeGen/CriticalAntiDepBreaker.cpp index 377b4712bea..f2bf9384e85 100644 --- a/lib/CodeGen/CriticalAntiDepBreaker.cpp +++ b/lib/CodeGen/CriticalAntiDepBreaker.cpp @@ -378,7 +378,7 @@ CriticalAntiDepBreaker::findSuitableFreeRegister(RegRefIter RegRefBegin, unsigned LastNewReg, const TargetRegisterClass *RC) { - ArrayRef Order = RegClassInfo.getOrder(RC); + ArrayRef Order = RegClassInfo.getOrder(RC); for (unsigned i = 0; i != Order.size(); ++i) { unsigned NewReg = Order[i]; // Don't replace a register with itself. diff --git a/lib/CodeGen/RegAllocFast.cpp b/lib/CodeGen/RegAllocFast.cpp index 88922169b30..db79284d245 100644 --- a/lib/CodeGen/RegAllocFast.cpp +++ b/lib/CodeGen/RegAllocFast.cpp @@ -527,10 +527,10 @@ RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineInstr *MI, } } - ArrayRef AO = RegClassInfo.getOrder(RC); + ArrayRef AO = RegClassInfo.getOrder(RC); // First try to find a completely free register. - for (ArrayRef::iterator I = AO.begin(), E = AO.end(); I != E; ++I) { + for (ArrayRef::iterator I = AO.begin(), E = AO.end(); I != E; ++I){ unsigned PhysReg = *I; if (PhysRegState[PhysReg] == regFree && !UsedInInstr.count(PhysReg)) { assignVirtToPhysReg(*LRI, PhysReg); @@ -542,7 +542,7 @@ RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineInstr *MI, << RC->getName() << "\n"); unsigned BestReg = 0, BestCost = spillImpossible; - for (ArrayRef::iterator I = AO.begin(), E = AO.end(); I != E; ++I) { + for (ArrayRef::iterator I = AO.begin(), E = AO.end(); I != E; ++I){ unsigned Cost = calcSpillCost(*I); DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n"); DEBUG(dbgs() << "\tCost: " << Cost << "\n"); diff --git a/lib/CodeGen/RegisterClassInfo.cpp b/lib/CodeGen/RegisterClassInfo.cpp index 805d2356730..bc48cfcc5c8 100644 --- a/lib/CodeGen/RegisterClassInfo.cpp +++ b/lib/CodeGen/RegisterClassInfo.cpp @@ -44,7 +44,7 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { } // Does this MF have different CSRs? - const uint16_t *CSR = TRI->getCalleeSavedRegs(MF); + const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); if (Update || CSR != CalleeSaved) { // Build a CSRNum map. Every CSR alias gets an entry pointing to the last // overlapping CSR. @@ -79,14 +79,14 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { unsigned NumRegs = RC->getNumRegs(); if (!RCI.Order) - RCI.Order.reset(new unsigned[NumRegs]); + RCI.Order.reset(new MCPhysReg[NumRegs]); unsigned N = 0; - SmallVector CSRAlias; + SmallVector CSRAlias; // FIXME: Once targets reserve registers instead of removing them from the // allocation order, we can simply use begin/end here. - ArrayRef RawOrder = RC->getRawAllocationOrder(*MF); + ArrayRef RawOrder = RC->getRawAllocationOrder(*MF); for (unsigned i = 0; i != RawOrder.size(); ++i) { unsigned PhysReg = RawOrder[i]; // Remove reserved registers from the allocation order. -- 2.34.1